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ISO7741: GanFet half-bridge isolation

Kevin Godfrey
Prodigy 40 points
Part Number: ISO7741
Other Parts Discussed in Thread: LMG3522EVM-042

Tool/software:

Hello folks! 

I am currently having some issues with a recent design, it is a 400V half bridge isolated with 2x ISO7741FDBQ. Upon further testing, I noticed that the VDD input of the LMG3522R030RQST became short circuited, apparently because there was a transient in the signal lanes between the bridge high side and common ground. Is there anything I might be overlooking ? 

TIA! 

 Sheet1.pdf

  • 0
    TI__Genius 17705 points

    Hi Kevin, 

    Thank you for your question!

    Sorry to hear you are having trouble! After looking at the schematic you have attached, I do not see anything of concern. Please make sure the decoupling capacitors are 0.1uF and less than 2mm away from VCC pin of isolator.

    Regarding the observations, can you please clarify what you mean in regards to the "transient" you mentioned? do you mean that there was an external transient applied? or did the isolator induce a transient of sorts?

    Regards,
    Aaditya Vittal

  • 0 in reply to Aaditya V.
    Prodigy 40 points

    Hello Aaditya! Thanks for the response! 

    The decoupling cap is definitely within that range. 

    I suspect that when the high side switches, the digital isolator is not being able to handle the common voltage to ground. I used a multimeter in resistance range (I know it is not adequate but works :) ) to probe between each isolated side. When the digital coupler is working fine, I was reading around 10Mohms and the faulty one was close to 100Mohms, apparently, after the fault, it really opened up the isolation coupling, resulting in that reading. 

    In the test we experienced this failure, another module started to show the same behavior, however we managed to shut it down before it damaged the GAN Fet.

    Best regards! 

  • 0 in reply to Kevin Godfrey
    TI__Genius 17705 points

    Hi Kevin, 

    Thank you for your response. 

    Please allow me an additional day to review this. In the mean time, can you please provide any other data such as PCB layout or waveforms? Since the switching of the FET is also of concern, these may be more helpful to suggest a solution as well.

    Regards,
    Aaditya V

  • 0 in reply to Aaditya V.
    Prodigy 40 points

    Hello Aaditya! Thanks for helping out!  This design is based on the LMG3522EVM-042 design, if it helps anything. Here are some screenshots of the layers for you to check out. 

    GAN_LAYERS.rar

    Best Regards! 

  • 0 in reply to Kevin Godfrey
    TI__Genius 17705 points

    Hi Kevin,

    Thank you for the PCB layout!

    I will review this as well and provide some additional input Monday next week.

    Regards,
    Aaditya Vittal

  • 0 in reply to Aaditya V.
    Prodigy 40 points

    Hi Aaditya.  I trust you are doing well?

    Do you perhaps have some inputs for me in the meantime?

  • 0 in reply to Kevin Godfrey
    TI__Genius 17705 points

    Hi Kevin, 

    Thanks for reaching out.

    After checking with my team and the information you have provided, this seems more related to the LMG3522 device. Therefore, I have notified the GaN team to further provide more information and support.

    Regards,
    Aaditya V.

  • 0 in reply to Aaditya V.
    TI__Expert 7435 points

    Hey Kevin,

    This can be caused by loop inductance in the high frequency power loop. During the layout phase we usually suggest layout where the ground return path follow directly below GaN devices on adjacent PCB layer (I have attached a slide that illustrates this). Since the PCB is already made, one step we can take to mitigate this is to lower the slew rate. In the schematic you are using the maximum turn on slew rate (20kohm RDRV resistor), we can try lowering this to the minimum (500kohm RDRV resistor) to see if the problem persists. 

    Best,

    Kyle Wolf