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ISOW7741: HV ADC Isolation. issues with SPI coms.

Tomas Begley
Prodigy 20 points
Part Number: ISOW7741
Other Parts Discussed in Thread: SN74LVC1G125

Tool/software:

Hi
I have designed a HV ADC board for voltage monitoring.
The idea was to daisy chain multiple of these boards over SPI to get multiple measurement inputs.

The issues I have come up against is that one board connected functions as expected.

with two boards connected the voltage of the data line gets pulled from 3.3v peak to 1.5v peak and occasionally wrong data is output.
with three boards connected the voltage of the data line gets pulled to 1v peak and no data arrives at all.

The chip selects are setup correctly but it is behaving like the chips are not correctly going to a high impedance state and pull the dataline down.

The current proposed fix is to put a tri state chip after the isolation chip on each board but ideally I would like to understand if it is a limitation of the isolation chip or if it is an issue with my implementation. 


Attached below are the schematics I have produced. The design was changed to operate on 5v while the test boards are 3.3v but this should not affect how the isolation chip interacts with the dataline.

 

  • +1
    Guru 317090 points

    The SDATA output of the ADC has three states. When the ADC is not active (/CS high), then the SDATA pin is disabled. This allows to connect multiple SDATA pins to the MISO pin of the controller at the same time.

    In this circuit, the OUTD pin of the isolator is always active, so you cannot connect them together. You have seen that the isolators of all the inactive ADCs pull the line low.

    You can either

    • combine all OUTD signals with an OR gate; or
    • disable all inactive signals with a SN74LVC1G125 buffer, controlled by the respective /CS signal; or
    • disable all inactive signals with EN_IO1, controlled by the inverted /CS signal (this forces OUTA/B low, so you should use the non-F isolator instead).