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ISO1228: open/gnd and open/28V inputs

Other Parts Discussed in Thread: ISO1228, ISO1211

Tool/software:

Dear TI Support,

I’m currently working with the ISO1228 device to interface field digital inputs (typically 24–28 VDC) to a microcontroller with isolation.

According to the functional table in Section 7.4 of the ISO1228 datasheet, when an input pin (INx) is in an open state, the output (OUTx) goes Low, as described:

“When INx is open, the output of the corresponding channel goes to Low.”

This behavior aligns well with our application. Specifically, we are using ISO1228 to detect discrete input signals in two configurations:

  • Open/GND: where GND = logic LOW, and open = logic HIGH

  • Open/28V: where 28 V = logic HIGH, and open = logic LOW

In both cases, open is treated as a valid logic state, not a fault condition. This is intentional and required behavior in our design.

However, I’ve seen some documentation or comments that suggest ISO1228 treats open inputs as undetermined or as a wire-break fault. To avoid any misunderstanding, could you please confirm the following:

  1. Is an open INx input consistently interpreted as logic LOW, per Table 7-1?

  2. Is this behavior safe and deterministic for production applications?

  3. Is there any internal timeout or protection logic that could interfere with intentionally floating inputs in open/GND or open/28V configurations?

We want to ensure ISO1228 behaves predictably when inputs are intentionally left open in these discrete signaling schemes.

I appreciate your support and clarification on this matter.

Best regards,

  • Hi again,

    As a continuation of my previous questions regarding the ISO1228, I would like to add two important clarifications:

    1. “Open” Input State as Shown in Datasheet Figures

    In Figure 10-1 and Figure 10-2 of the ISO1228 datasheet, the INx pin is shown connected through series resistors to a mechanical switch, where the opposite terminal is either pulled to GND or 24 V — and when the switch is open, the INx input is left floating.

    This clearly shows that the “open” input condition is expected and intentional in both sink and source type configurations. Could you please confirm that:

    The open input condition, as shown in these figures, is officially supported and will be interpreted deterministically as a valid logic LOW input by the ISO1228?

    In our use case, the open state is not a fault but a functional logic condition — so it’s important to verify that the device does not treat this as undefined or erroneous.

    2. CRC Error Conditions and Recovery Behavior

    Additionally, we would like to ask about the robustness of ISO1228 under harsh electrical conditions.

    Under what circumstances can CRC or internal data integrity errors occur in the ISO1228?
    For example, are any of the following known to cause issues:

    • High ambient temperature

    • Magnetic fields

    • Electrical transients or noise

    • ESD events

    And in case a CRC fault or isolation communication error does occur:

    • Does the device enter a fault state, or is there a risk of internal lock-up?

    • Would a hardware reset be required to recover from such a situation, or is it self-recovering?

      We are designing for industrial environments and want to ensure the ISO1228 remains reliable and responsive under adverse conditions.

    Thank you again for your continued support.

    ismail

  • Hi Ismail,

    Thanks for reaching out. Please give me an additional 24 hours to review and respond.

    Regards,
    Aaditya V

  • Hi Aaditya,

    Sure, I will be waiting your reply.

    Thanks and regards.

    İsmail

  • Hi Sam, 

    Thanks for your patience.

    Please see the answers to your questions below:

    • Is an open INx input consistently interpreted as logic LOW, per Table 7-1?

    • Is this behavior safe and deterministic for production applications?

    • Is there any internal timeout or protection logic that could interfere with intentionally floating inputs in open/GND or open/28V configurations?

    Yes, when INx is open, the output logic state will be LOW. This behavior is consistent with all ISO1228 devices. In terms of the internal timeout or protection logic, I believe that this device does not have those features and simply will stay LOW state when INx is open. I will confirm with my team in regards to this and respond.

    Regards,
    Aaditya V

  • Hi Aaditya,

    Thank you for your response and for checking internally regarding the behavior of open INx inputs.

    This clarification is highly valuable for us, as it plays a critical role in our system design. We are considering using the ISO1228 in configurations where inputs may be intentionally left open under certain conditions, so it is important for us to ensure that the device's behavior in these states is deterministic and safe for production.

    We look forward to your confirmation regarding the absence of any internal timeout or protection logic that could affect this open-input behavior.

    Thanks again for your support.

    Best regards,

  • Hi Aaditya,

    I came across the following case regarding a question on the ISO1211. I understand that ISO1211 is different from the ISO12128, but one of the TI experts responded with the following:

    "An example device that is meant for isolating field digital input signals is ISO1211. It doesn't read an OPEN but reads a high voltage (like 24V, 48V, 60V, etc.) and 0V and provides isolated logic output to an MCU."

    This case was particularly relevant to my own situation and helped clarify some aspects:
    https://e2e.ti.com/support/isolation-group/isolation/f/isolation-forum/888580/isolation-for-discrete-input-with-levels---open-or-ground/3285445?tisearch=e2e-sitesearch&keymatch=ISO1211%25252520open#3285445

    I thought it might be helpful to share, as it directly relates to the behavior I'm trying to confirm.

    Best regards,

  • Hi Sam,

    Thanks for your responses. 

    The ISO1211 and the ISO1228 are completely different devices and therefore have different behaviors when input is present versus when it is not. Allow me to check with my team and respond by the end of the week. If possible, would you mind please putting the questions you have in a bullet point list so that its a bit easier to read?

    Regards,
    Aaditya V

  • Hi Aaditya,

    Thank you for your response and the clarification regarding the ISO1211 and ISO1228.

    Please do take your time to check with your team.

    I’ve listed my questions below in bullet point format for easier reference, as requested:

    Questions Regarding ISO1228 Behavior:

    • Open INx Input Behavior:
      According to section 7.4 of the ISO1228 datasheet, if an INx pin is left floating (unconnected), will the corresponding OUTx always be interpreted as logic LOW?

    • Interpretation of "Open" in Datasheet Figures:
      In Figures 10-1 and 10-2 of the ISO1228 datasheet, mechanical switches connect INx to either GND or 24V. If the switch is open (floating input), is this deterministically treated by the device as a logic LOW?

    • Reliability for Production Use:
      Is this default LOW behavior for open inputs safe and deterministic enough to be relied upon in production applications?

    • Internal Timeout or Protective Logic:
      Does the ISO1228 implement any internal timeout, filtering, or safety mechanisms that might affect how the device handles open-to-GND or open-to-28V configurations?

    • CRC or Internal Fault Behavior:
      Could the ISO1228 generate CRC or internal integrity errors due to environmental conditions such as:
      – High ambient temperature
      – Strong magnetic fields
      – Electrical transients or interference
      – Electrostatic discharge (ESD)

    • Recovery from Faults:
      If such a fault does occur,
      – Does the device enter a fault or lock-up condition?
      – Would a hardware reset be required to recover, or can the device self-recover?

    Thank and regards

    Sam

  • Hi Sam,

    Thanks for the list. I will discuss this with my team and provide some information in regards to your questions. Please give us until mid next week to respond.

    Regards,
    Aaditya V.

  • Hi Aaditya,

    Thanks for the update. I appreciate the timeline, but I’d like to kindly highlight the importance of not delaying the responses further, as this is currently blocking our next steps.

    Looking forward to hearing from you by mid next week as mentioned.

    Best regards,

  • Hi Sam,

    I understand  and sorry that this is taking long.  I will be asking some experts tomorrow in regards to your questions. I will definitely let you know as soon as possible.

    Regards,
    Aaditya V

  • Hello Sam, 

    Please see our answers below:

    • Open INx Input Behavior:
      According to section 7.4 of the ISO1228 datasheet, if an INx pin is left floating (unconnected), will the corresponding OUTx always be interpreted as logic LOW?
      • Yes, this is the standard setup for a the typical feild sensors that ISO1228 is designed for since this enables wire-break detection.
      • A given OUTx will be low when the corresponding INx is open (and OUT_EN is enabled).
      • Aaditya showed this condition in the truth table earlier
    • Interpretation of "Open" in Datasheet Figures:
      In Figures 10-1 and 10-2 of the ISO1228 datasheet, mechanical switches connect INx to either GND or 24V. If the switch is open (floating input), is this deterministically treated by the device as a logic LOW?
      • Yes, an open INx is treated as a logic low. 
    • Reliability for Production Use:
      Is this default LOW behavior for open inputs safe and deterministic enough to be relied upon in production applications?
      • Yes, this is reliable. The internal current source of ISO1228 will efficiently drain the current on the floating input.
    • Internal Timeout or Protective Logic:
      Does the ISO1228 implement any internal timeout, filtering, or safety mechanisms that might affect how the device handles open-to-GND or open-to-28V configurations?
      • General comments, and fault register map shown below:
        •   
        • There are protection features on the ISO1228, and they should not affect how the input is handled since they can be programmed for your needs. The main feature would be the (7.3.6) Digital Low Pass Filters (other features can be seen in 7.3 Feature Description).
          CRC or Internal Fault Behavior: Could the ISO1228 generate CRC or internal integrity errors due to environmental conditions such as:
        • The fault protections features (7.3.5 FAULT Indication) are available when serial (SPI-mode) is enabled. A presence of a fault can also be detected using the nFault pin in parallel mode. How to Dynamically Switch Between Serial and Parallel Modes Using ISO1228 shows a use case where a fault is detected in parallel mode and then further investigated using the fault register in serial mode. 
      • High ambient temperature
        • Yes, there is a device over-temperature fault feature 
      • Strong magnetic fields
        • Not exactly, however there is a CRC to detect data errors from data transmitted accross the isolation barrier.
      • Electrical transients or interference
        • same as above 
      • Electrostatic discharge (ESD)
        • There is a level of Integrated IEC ESD and Surge Protection when using surge-proof resistors (7.3.1 Surge Protection). Otherwise, a TVS diode at the input terminal will protect from most system-level ESD.  
    • Recovery from Faults: If such a fault does occur,
      • Does the device enter a fault or lock-up condition?
        • The fault will be recorded in the fault register however the device will operate as normal (no lock up). The App note above describes the behavior under fault conditions. Dynamically switching between modes can be used for further. Otherwise, any fault can be detected on the nFault pin in parrallel mode. 
      • Would a hardware reset be required to recover, or can the device self-recover?
        • ISO1228 will self-recover once the fault condition is cleared (assuming the fault did not cause device or system damage). nFault pin will reset when the fault register is read. 

    Best,
    Andrew