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SN6505B: Enable pin suitability for RC timer

Jack Terrell
Prodigy 76 points
Part Number: SN6505B

Tool/software:

Team,

I am looking into using an RC element as a low-cost timer to delay the startup of a fairly standard SN6505B setup.  The delay does not need to be precise; the length just must be more than a certain minimum.  From a prior post, I can tell that there is a 500kOhm pull-down resistor on EN (https://e2e.ti.com/support/isolation-group/isolation/f/isolation-forum/970077/sn6505b-q1-en-pin-pull-down-resistor).

Here are my questions:

1. During power-down, is there a potential for damage if the EN pin still has voltage on it after Vcc has already fallen to zero?  This voltage would be from the RC timing capacitor; is there a maximum safe capacitance?

2. Does the SN6505B draw additional current when the EN pin is between the low and high positions?  If so, how much?  This is common on CMOS gates.  I couldn't find a TI example, but I came across this graph on Nexperia's 74LVC1G17.


3. Does the SN6505B have a significant (>5uA) bias current on the EN pin other than the 500 kOhm pull-down current (which is predictable by modeling as a resistor)?

  • 0
    Prodigy 76 points

    Also, this is my schematic:

    Thanks,

    -Jack

  • 0 in reply to Jack Terrell
    TI__Genius 10370 points

    Hi Jack,

    The device have internal ESD diode on pins and is mentioned in datasheet, the current to this pin needs to limit in absence of Vcc. 

    The device will turn On once the threshold reaches 0.7V. Once the EN pin transitions from Low to High, the gate drive of the output power-MOSFET is gradually increased over a period of time from 0 V to VCC.

    Device to device it can vary. The max threshold for Enable On is 0.7V and Off is 0.3V.  

    The leakage current mentioned for EN pin in datasheet is 20uA. 

    Thanks. 

  • 0 in reply to Shinu.V.Mathew
    Prodigy 76 points

    The internal ESD diode is helpful, as it indicates that the EN pin would be clamped in this case.  To follow up, is there a maximum current limit for the is internal ESD diode on EN?  This would allow me to put a series resistor between the RC timer for EN, but I need to know the limit to do so.

    In terms of the "halfway-on" Icc rise, this wouldn't be related to the thresholds or the leakage observed at the pin, but rather the logic-gate-like input structure of EN.  From what I understand, this must be a Schmitt trigger of some sort, as normal logic gates don't have hysteresis like this one.  If it were present, the excess current comes from the positive and negative transistors both being partially on when the EN input is about 0.3*Vcc to 0.7*Vcc.  For a relevant E2E post discussing this Icc rise in a different context, here's one from the Logic forum:  e2e.ti.com/.../sn74hcs126-reducing-shoot-through-current-by-schmitt-trigger-input

    I also interpreted the datasheet for device on/off as 0.7*Vcc and 0.3*Vcc instead of 0.7V and 0.3V.  Due to the ramp rate of my input voltage, I am confident that the RC will not reach 0.7*Vcc anytime before the Vcc=2.25V positive-going UVLO threshold.

    Thanks,

    -Jack

  • 0 in reply to Jack Terrell
    TI__Genius 10370 points

    Hi Jack,

    I will check on internal ESD diode max rating and update.

    Thanks.