SN6507: SYNC mode causing latchup

Hi team,

Adding a link to the reference to a previous e2e forum post mentioned in this post:

https://e2e.ti.com/support/isolation-group/isolation/f/isolation-forum/1421326/sn6507dgqevm-latched-recoverable-only-by-input-power-cycle?tisearch=e2e-sitesearch&keymatch=sn6507

Best,

Cam

Hi Prateek,

Th SN6507-Q1 (automotive) data sheet in 8.4.4 says "The device cannot automatically change from SYNC mode to switching frequency control using the internal oscillator or resistor-programmable switching frequency mode. If a valid external CLK signal is not present, the output will stop switching, and a power cycle will be required to change the switching mode back to using the internal oscillator or the adjustable switching frequency using RCLK."  That pretty accurately describes the operation of the SN6507 that came on my SN6507DGQEVM Eval board (with the further observation that the switching mode can be changed by strobing the EN/UVLO pin as an alternative to cycling power).  Does TI put the automotive version on the Eval boards?  Note that 8.4.4 of the SN6507 (non-automotive) data sheet says the opposite: "The device can automatically changes from SYNC mode to the internal or resistor CLK mode, if a valid external clock is not present for a certain period of time (tCLKTIMER). Similarly, when the part transitions from internal or resistor controlled CLK mode to SYNC mode, there will be five CLK cycles delay for external CLK detection."  This is either untrue, or I don't have the non-automotive SN6507 on my Eval board.

Your response to my initial posting suggested that the SN6507 would automatically switch from external clock to internal clock (the 1MHz when the CLK pin is grounded) even though it WOULDN'T automatically switch from external clock to the resistor-controlled internal clock mode.  That is NOT what I observe with the Eval board.  It doesn't automatically switch from external to internal clock mode regardless of whether the internal mode is a resistor to ground or a short to ground.  What is the significance of your bolded "when an MCU is connected"?  What is the "MCU" doing that I'm not also doing with the Eval board.

Note that I do NOT have the same issue as that similar post (with the "false clock" noise).  I am not trying to run in a resistor-controlled internal clock mode and being thwarted by noise on the CLK line that puts it into SYNC mode and locks it up.  I WANT to run it in external clock mode, but (if at all possible) I also want to have a shunt resistor present so that prior to when the clock is applied the SN6507 is already running near the desired frequency and that if the external clock should ever fail (in a high-impedance state) that the SN6507 would resume that internal resistor0controlled clock frequency.  

So... I still have the following questions:

1) Is it true that the non-automotive and automotive parts behave differently with respect to that SYNC mode? 

2) Is it true that the non-automotive and automotive parts are identically marked?

3) Which version (automotive or non-automotive) of SN6507 is installed in the SN6507DGQEVM Eval board?

4) Is it really TI’s recommendation (see 8.4.4 of either datasheet) that for external clocking the clock input be high impedance prior to the SN6507’s power being applied? If so, for how long?  Can the clock and power be applied “simultaneously”?  Note that with the EVAL board, the SN6507 (whichever version it is) seems not to care (at least not so far) if the clock is applied long before the power.  What am I risking by not heeding this particular recommendation?

Hi Prateek,

So, to summarize, the answers to my questions are:

1) Is it true that the non-automotive and automotive parts behave differently with respect to that SYNC mode? [No.  They behave the way that is described in section 8.4.4 of the SN6507-Q1 datasheet.  The SN6507 datasheet is wrong.]

2) Is it true that the non-automotive and automotive parts are identically marked?  [No confirmation, but that's what the datasheets seem to say.  If they behave identically, then having the same marking isn't a serious concern of mine.]

3) Which version (automotive or non-automotive) of SN6507 is installed in the SN6507DGQEVM Eval board?  [No answer.  If they behave identically, then knowing which part is in the Eval board isn't as important to me.]

4) Is it really TI’s recommendation (see 8.4.4 of either datasheet) that for external clocking the clock input be high impedance prior to the SN6507’s power being applied? [Yes.] If so, for how long? [Not really answered.  See below.]  Can the clock and power be applied “simultaneously”?  [Not really answered.  See below.]  Note that with the EVAL board, the SN6507 (whichever version it is) seems not to care (at least not so far) if the clock is applied long before the power.  What am I risking by not heeding this particular recommendation?  [The primary issue is the protection of the internal ESD diodes.]

Let's talk about the issue of keeping the external clock input high impedance until after the SN6507 is powered up.  I asked whether that was necessary (as my testing with the Eval board suggested that it wasn't).  I asked for how long after the SN6507 was powered up did the CLK input need to remain high impedance.  I asked what the risk was of not following TI's recommendation but just applying the clock simultaneously with the powering up of the SN6507.  Your response repeats the recommendation in the datasheet without saying what I risk by applying the clock simultaneously with applying power, but adds info about "20us to check for valid input at CLK pin".  I don't see this "20us" as being an answer to my question of how long after power up the CLK pin needs to remain high impedance.  In fact, this sounds like section 8.4.4 of the non-automotive datasheet (which you acknowledge is wrong, but maybe not this portion of it) that says "when the part transitions from internal or resistor controlled CLK mode to SYNC mode, there will be five CLK cycles delay for external CLK detection" - but with 20us substituted for five clock cycles.  This would seem to be the time AFTER application of the external clock before the SN6507 reacts to that external clock whereas I was asking for the required time BEFORE the application of the external clock (but after power-up of the SN6507).  

I was concerned that if the clock is applied too soon after the SN6507 is powered up that there is some risk that the external clock might not be properly detected and synchronized with (not that I've seen that with the Eval board).  Is that a risk?  Is there some other risk of incorrect SN6507 operation from that external clock being applied too soon after power-ON that I should be aware of?

The last line of your response indicates that one concern about applying the clock BEFORE the SN6507 is fully powered up is for the possible damage of the internal ESD diodes (and that is perfectly understandable).  If that is the ONLY real concern (is it?), then aren't there other ways to protect those diodes?  While not in the Absolute Max section of either of the SN6507 datasheets, other ICs often have a max voltage range for input pins (typically -0.5V to Vdd +0.5V) and also a maximum input current if that input voltage range is exceeded.  Such devices can be protected by inserting a series resistor at the input to limit that maximum input current through those internal ESD diodes.  Can you provide such information for the SN6507 (the max allowed current for the internal ESD diodes on the CLK pin - especially the one going to Vdd) so that I can add the appropriate series resistor between my external clock and the CLK pin?  Or is there some reason why you would recommend against adding such a series resistor?

Thanks,

Charles