Other Parts Discussed in Thread: SN6505A-Q1, SN6501-Q1, SN6507, SN6505A, SN6505B, SN6505B-Q1, SN6507-Q1, SN6501, SN6505D-Q1
SN650xx Family – Frequently Asked Questions (FAQ)
This home page is for common questions in relation to the SN6501, SN6501-Q1, SN6505A, SN6505A-Q1, SN6505B, SN6505B-Q1, SN6505D-Q1, SN6507, SN6507-Q1.
FAQs
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1. How can EMI and switch-node ringing be reduced in SN650xx designs?
Electromagnetic interference (EMI) and switch-node ringing can be mitigated by following these best practices:
- Add a RC snubber circuit across the transformer primary or switch nodes, as required, to damp high-frequency ringing. See App-note
- Strictly follow PCB layout guidelines given in the section 11.Layout of datasheet.
- Place a 0.1 µF ceramic decoupling capacitor close to the VCC pin of the SN650xx device.
- Place a 10 µF bulk capacitor close to the transformer primary supply pin.
Proper component placement and short return paths are critical for minimizing noise.
2. Can an SN650xx device drive multiple transformers?
Yes, but with some limitations:
- Parallel Connection : SN650xx device can drive multiple transformers in parallel, provided that the total primary current remains below the device’s specified primary-side current drive capability.
- Series Connection : Series connection of transformers is not recommended. This configuration can degrade overall efficiency and may lead to excessive heating and reliability concerns.
3. How should a transformer be selected for an SN650xx design?
Transformer selection is critical to performance and reliability. Use the following approach:
- Utilize the TI Transformer Calculator Tool available on the SN6501 product page.
- Follow the Detailed transformer design and selection procedure outlined in the device datasheet.
4. Why does switching stop or latch-up behaviour occur in some designs?
If switching stops or latch-up behaviour is observed, the most common cause is an invalid or unstable external clock signal.
Recommended solution:
- Use a capacitor value less than 100 pF on the CLK pin.
Reason:
- Excessive capacitance on the CLK pin can prevent proper detection of the external clock, causing the device to stop switching.
- Refer to this E2E thread - SN6507: SYNC mode causing Latchup
SN650xx device datasheet
TI application notes related to isolated push pull based power supplies
- SN6507 – Webench Design
- How to Reduce Emissions in Push-Pull Isolated Power Supplies (Rev. A).
- Push-Pull Converter design
- Input Filter Design for Switching Power Supplies
- Push-pull converter simplifies isolated power supply design in HEV/EV systems
- System-Level ESD Protection Guide (Rev. E)
TI Evaluation modules
Spice models
- SN6501 Unencrypted PSpice Transient Model Package (Rev. A)
- SN6505B PSpice Transient Model (Rev. B)
- SN6507-20241101.zip
Cad Symbols, footprints & 3D models
- SN6501 - Ultra Librarian
- SN6505x - Ultra Librarian
- SN6507 - Ultra Librarian