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Dear Team,
My customer used ISOW7841, but it cannot pass EMI testing.
So they would like to follow the app note slla368a to implement stitching capacitance between GND and VCC.
Their PCB has 6 layer, and the space between each layer is fixed. The PCB design as below:
Layer 1 -------------------- (TOP)
d=0.06 mm
Layer 2 --------------------
d=0.1 mm
Layer 3 --------------------
d=1 mm
Layer 4 --------------------
d=0.1 mm
Layer 5 --------------------
d=0.06 mm
Layer 6 -------------------- (Bottom)
In the app note, its example is 0.66 mm. But due to the customer cannot change their PCB design, so we only can choose 0.1 mm spacing (Layer 2=GND, Layer 3=VCC) or 1 mm spacing (Layer 3=GND, Layer 4=VCC). 1mm spacing will have higher voltage rating but lower capacitance, am I correct? Which one is better?
If I choose 1 mm spacing, then PCB design will have three ground layer as below.
Layer 1 -------------------- (TOP)
d=0.06 mm
Layer 2 -------------------- (GND)
d=0.1 mm
Layer 3 -------------------- (GND)
d=1 mm
Layer 4 -------------------- (VCC)
d=0.1 mm
Layer 5 -------------------- (GND)
d=0.06 mm
Layer 6 -------------------- (Bottom)
Is this the best solution? Please help to advise.
