Original question:
ISO7741: What's the behavior when IC is shutdown and with external power
Hi Isolation experts,
When looking at section 7.2 of the ISO7741 datasheet - my customer is wondering if the ESD testing is performed when VCC1 and VCC2 are connected to power or is this test performed when there is no external power, just the ESD event?
Also, if it is different between JS-001, JESD22-C101, and IEC 61000-4-2 then please clarify the power state of each.
Thank you!!
Reed
Hi Reed,
Thanks for reaching out to us.
HBM and CDM ESD tests are the models defined to represent ESD events in an ESD controlled factory assembly & test environment. In such an environment, handling of device primarily involves the device being assembled onto the PCB where the device is usually unpowered. Similarly, HBM and CDM, which are the predefined waveform patterns with controlled energy output, are applied onto device I/Os with the device unpowered. These ESD pulses are applied to all the I/Os with respect to their neighboring and GND pins.
IEC 61000-4-2 ESD is quite different from HBM and CDM. This is an ESD event that can occur on a product when the product is in use in the actual applications. IEC ESD pulses contain much more energy than HBM or CDM ESD pulses. IEC ESD test is also conducted on a customer product at the end product level and the ESD pulse applied on the external terminals of customer product may or may not reach the digital isolator. If IEC ESD pulse reaches device pins, it usually appears between the isolator side1 and side2 pins.
Since IEC ESD is primarily defined for end product and not for and individual component, there is not a standard approach defined in IEC 61000-4-2 for testing a digital isolator. Hence, we have defined our own approach to test for IEC ESD which we believe is the worst case test condition. In our IEC ESD test setup, we connect together all the pins on side1 to form one terminal and connect all the pins on side2 to form another terminals and then applied IEC ESD pulse across these two terminals. The below picture shows the 2-pin test configuration for IEC ESD.
I am copying below a peak current plot for HBM, CDM and IEC ESD pulses. The requirement for HBM is usually <2kV, for CDM <1k and IEC ESD it can be upto 8kV or even higher. The peak currents of commonly occurring ESD levels are plotted in the below image.
I am also copying below couple links to useful ESD related blogs.
Let me know if you have any questions, thank you.
Regards,
Koteshwar Rao
