ISO7041: Undetermined output when supply is <1.54V- for how long?

Part Number: ISO7041

Hi,

Question from my customer-

We’ve started testing the ISO7041 on some newer designs, mostly due to its low supply current.  Normally we use a ADI part.

 

One of the issues with the AD parts is they sometimes glitch as the power supply on the output side is ramping up (usually while it’s below I think 2V or so).

 

I see in the datasheet for the ISO7041 that the output is undetermined when the output supply is <1.54V and that the tPU (Time from UVLO to valid output data) is 1-5ms.  Does this mean that the output is undetermined for 1-5ms after the supply is >1.54V?  Or does it mean the output is defined high (for the non-“F” version) after 1.54V and then takes the correct state (based on the input side) 1-5ms later?

 

Basically what I’d like to know is: can I remove the circuit we use to filter the AD glitches if we use this TI part or should I leave it in?

Thanks,

Lauren

  • Hi Lauren,

    Thanks for reaching out and sharing detailed customer question. Please see my inputs below, thanks.

    I see in the datasheet for the ISO7041 that the output is undetermined when the output supply is <1.54V and that the tPU (Time from UVLO to valid output data) is 1-5ms.  Does this mean that the output is undetermined for 1-5ms after the supply is >1.54V?  Or does it mean the output is defined high (for the non-“F” version) after 1.54V and then takes the correct state (based on the input side) 1-5ms later?

    When VCC is <1.54V, the device is as good as unpowered. If VCC is closer to 0V then the output is clearly going to be 0V but if the input is non-zero and is <1.54V then some sections of the device will still be powered and waiting for valid supply to appear. For this reason, it is possible to see an intermediate voltage at the outputs when VCC is non-zero but is still <1.54V.
    Once VCC goes up and the voltage is in the UVLO range (between 1.54V and 1.71V), device gets fully powered-up. From the point VCC hits UVLO voltage, it will take upto 5ms time for the outputs to start following the input assuming ENx is LOW. During these 5ms the device is still not fully powered and hence the outputs are still going to remain like they were when device was unpowered, i.e., Undetermined.

    Basically what I’d like to know is: can I remove the circuit we use to filter the AD glitches if we use this TI part or should I leave it in?

    Could you please share what filter circuit did you add to filter out the glitches so that I can comment if that would be necessary for ISO7041? Thanks.


    Regards,
    Koteshwar Rao

  • Hi Lauren,

    Please do help us with the filter circuit so that I can comment if that is necessary for ISO7041, thanks.


    Regards,
    Koteshwar Rao

  • Hello,

    The feedback I got was-

    We usually filter the glitches by putting a UVLO chip on the board that defines it’s state once the supply hits about 0.8V.  Then it continues to hold everything off for a few ms after the supply is “good”.

     

    To clarify the power up sequence on the ISO7041:

    -Below 1.54V, output could be anything from 0 – VCC.

    -Above 1.54V, but before 5ms, output could be anything from 0 – VCC (even if VCC is already 5V).

    -Above 1.54V and after 5ms, normal operation.

     

    We typically set up our logic signals so that, on power up, they match the default state of the isolators.  That way there should be a seamless transition from the isolator powering up to the isolator taking the power up state of the logic signal going to it.  If the ISO7041 takes it’s default state as soon as it hits 1.54V, that would be perfect for us and we could remove the external UVLO.  Or does what you’re saying mean even if the VCC supply to the isolator turned on instantaneously, we’d still need to wait up to 5ms before we can be confident the output is in the default state (whether based on the input or the isolator default)?

  • Hi Lauren,

    Thanks for sharing additional customer inputs and clarifications.

    -Below 1.54V, output could be anything from 0 – VCC.

    That's correct. Since VCC itself is <1.54V here, the output is going to be <<1.54V.

    -Above 1.54V, but before 5ms, output could be anything from 0 – VCC (even if VCC is already 5V).

    Above 1.54V, the internal circuits are fairly powered and hence, we don't expect intermediate voltages. The outputs will be either Hi-Z or start following the input in that 5ms time.

    -Above 1.54V and after 5ms, normal operation.

    This is accurate.

    If the ISO7041 takes it’s default state as soon as it hits 1.54V, that would be perfect for us and we could remove the external UVLO.  Or does what you’re saying mean even if the VCC supply to the isolator turned on instantaneously, we’d still need to wait up to 5ms before we can be confident the output is in the default state (whether based on the input or the isolator default)?

    The ISO7041 doesn't take default state after power-up, it straight goes to follow the input after it is powered-up within the 5ms time. Yes, you would need wait up till the 5ms time because that is the worst-case power-up time.

    Since you already tie the inputs to the default value and your concern about glitches is during power-up, I can confidently say that we do not expect any glitches at the output during the 5ms power-up time provided the input supply ramp time is not too slow. i.e., ramp time is <10ms. During the power-up time, we expect the outputs to be either in Hi-Z or follow the inputs.
    If this meets your requirement then you can choose not to have the UVLO circuit.

    Let me know if you have any further questions, thanks.


    Regards,
    Koteshwar Rao