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ISO7041: SPI application, vs undetermined state

Bart
Expert 6460 points
Part Number: ISO7041
Other Parts Discussed in Thread: ISO7741

Team,

We would like to use ISO7041 as SPI isolation. Having some doubts regarding MISO line.

On VCC2 side we have a devie, which after deactivation of CS pin, will put the MISO pin in HiZ state. What state can we expect on VCC1 side (ISO7041)? 

Having a memory placed on VCC1 side, we would like to avoid the situation where ISO7041 would block the communication with the memory (or also when if VCC2 is not present).

Thanks for clarifying.

  • 0
    TI__Expert 6955 points

    Bart,

    From my understanding, the situation in question is when the channel input is high z and therefore the output is not known. Taking a look at the device modes from the datasheet, I believe this situation would create an undetermined output. 

    To mitigate this, I would implement a pulldown or pullup resistor at the channel input in order to force the input state high or low at all times.

    Respectfully,

    Lucas

  • 0 in reply to Lucas Schulte9
    TI__Intellectual 1960 points

    Hi Bart:

    Just to add to Lucas's response -

    If you have additional SPI devices on the VCC1 side of the isolator (like memory in your application), isolator OUTD must be at high-impedance when left side device SPI registers are being read. Unfortunately, there is no disable for OUTD of ISO7041. You may consider ISO7741 for this application. ISO7741 is P2P with ISO7041. Please make sure that EN1 (pin 7) of ISO7741 is driven low when VCC1 side device SPI registers are being read.

    Regards,

    Dushmantha

  • 0 in reply to Dushmantha Rajapaksha
    TI__Expert 6460 points

    Hi Dushmantha, Lucas,

    thanks for your feedback. Unfortunately ISO7741 can't be used due to Icc currents.

    Is the mitigation that Lucas mentioned the best method to adapt ISO7041 here?

  • 0 in reply to Bart
    TI__Expert 6955 points

    Bart,

    We would like to make sure the ISO7041 along with a pulldown or pullup resistor would work when considering the SPI network as a whole. Would you be able to share a high-level block diagram of the SPI communication bus in your system that includes SPI devices as well as any buffer elements, such as isolation devices, that would also be on the SPI bus?

    Respectfully,

    Lucas

  • 0 in reply to Lucas Schulte9
    TI__Expert 6955 points

    Bart,

    I haven't heard back from you. I hope you have been able to resolve this. I am marking this as resolved for now but please feel free to open a related thread if you still need help.

    Respectfully,

    Lucas