TPIC74100-Q1 waveform in power off

Atsushi Yamauchi

Genius 4810 points

Other Parts Discussed in Thread: TPIC74100-Q1

I fixed waveforn in ramp up (add 1uF capacitor).

But there is the small peak in the power off.

I attacked the file.

6835.TPIC74100_power_off.pdf

I have questions.

1. Why is it occured (in the red circle at CLP pin)? What is the cause?

2. Does TPIC74100-Q1 (CLP pin) have the peak in power off?

3. Are there any solutions for improving the peak?

Best regards,

Atsushi Yamauchi

over 11 years ago

0 Mahmoud Harmouch over 11 years ago

TI__Mastermind 26910 points

Bench test conclusion

•CLP has internal pull up circuit so device can operate in low power mode and PWM mode depends on load current

•Floating CLP voltage is not because of crosstalk

•CLP voltage can increase to 5V steady in PWM mode

•During power down and before device turning off boost circuit is active

•When device is off so Q3 transistor Cboot1 keeps residual voltage (see scope picture)

•It seems the same amount of residual voltage in on CLP

6102.TPIC74100_CLP floating.pptx

0 Atsushi Yamauchi over 11 years ago in reply to Mahmoud Harmouch

Genius 4810 points

Dear Mahmoud-san,

Thank you for yuor quick response!

I have a question.

Can we improve the wave form? Or are not there any ways to avoid it?

Best regards,

Atsushi Yamauchi

0 Mahmoud Harmouch over 11 years ago in reply to Atsushi Yamauchi

TI__Mastermind 26910 points

Yamaushi-san, I believe it can be improved by lowering the CLP pull down resistor

0 Atsushi Yamauchi over 11 years ago in reply to Mahmoud Harmouch

Genius 4810 points

Dear Mahmoud-san,

Thank you for your help.

I have received the waveform in power off (spread the time axis).
In the waveform, VIN has a peak too.

I have understand the cause of the peak at CLP pinm but don't understand the cause of the peak of VIN.
I attached the waveform.

2543.TPIC74100_Q1_CLP_VIN_in_power_off.pdf

Could you please advise to me?

Best regards,

Atsushi Yamauchi

0 Mahmoud Harmouch over 11 years ago in reply to Atsushi Yamauchi

TI__Mastermind 26910 points

I guess you meant Vdriver pin 4. If you look at the internal circuit there is path from VOUT through Q4 transistor, inductor between L1 and L2 pins and substrate diode of Q1. I believe the peak voltage on Vdriver is due to residual voltage on VOUT

0 Atsushi Yamauchi over 11 years ago in reply to Mahmoud Harmouch

Genius 4810 points

I'm sorry for late reply.

I understood the cause of the peak in Vriver pin.

I have a question. Are there any solution for the peak of Vriver pin?

Best regards,

Atsushi Yamauchi

0 Mahmoud Harmouch over 11 years ago in reply to Atsushi Yamauchi

TI__Mastermind 26910 points

The peak on Vdriver depends on the VOUT decay. Higher capacitor on Vdriver will lower the peak

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TPIC74100-Q1 waveform in power off