I have been migrating a project from DSP/BIOS to SYS/BIOS for the 28335 and have run into another question. In the legacy code, there is a call within main at the beginning of the code to a user init code that configures the PLL.
I'm battling an issue where my application never reaches the breakpoint at main() and when I let the program run and halt it, I often halt it when it is in the middle of this code, so I'm wondering if it is the culprit. In this function is the following:
//--- Configure the PLL
// Note: The DSP/BIOS configuration tool can also be used to initialize the PLL
// instead of doing the initialization here.
// Make sure the PLL is not running in limp mode
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1)
{ // PLL is not running in limp mode
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; // Turn off missing clock detect before changing PLLCR
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0; // DIVSEL must be 0 or 1 (/4 CLKIN mode) before changing PLLCR
SysCtrlRegs.PLLCR.bit.DIV = 0x000A; // PLLx10/4 (because DIVSEL is /4)
// Wait for PLL to lock.
// During this time the CPU will run at OSCCLK/2 until the PLL is stable.
// Once the PLL is stable the CPU will automatically switch to the new PLL value.
// Code is not required to sit and wait for the PLL to lock. However,
// if the code does anything that is timing critical (e.g. something that
// relies on the CPU clock frequency to be at speed), then it is best to wait
// until PLL lock is complete. The watchdog should be disabled before this loop
// (e.g., as was done above), or fed within the loop.
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) // Wait for PLLLOCKS bit to set
{
SysCtrlRegs.WDKEY = 0x0055; // Service the watchdog while waiting
SysCtrlRegs.WDKEY = 0x00AA; // in case the user enabled it.
}
// After the PLL has locked, we are running in PLLx10/4 mode (since DIVSEL is /4).
// We can now enable the missing clock detect circuitry, and also change DIVSEL
// to /2. In this example, we will wait a bit of time to let inrush currents settle,
// and then change DIVSEL from /4 to /2. This is only an example. The amount of
// time you need to wait depends on the power supply feeding the DSP (i.e., how much
// voltage droop occurs due to the inrush currents, and how long it takes the
// voltage regulators to recover).
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0; // Enable missing clock detect circuitry
DelayUs(20/2); // Wait 20 us (just an example). Remember we're running
// at half-speed here, so divide function argument by 2.
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0x2; // Change to /2 mode
}
else
{ // PLL is running in limp mode
// User should replace the below with a call to an appropriate function,
// for example shutdown the system (since something is very wrong!).
Reset();
}
I attemped to have SYS/BIOS configure the PLL by checking the box in the boot section of the cfg file. 
I commented out the above code, and checked the box and tried to build. Naturally it failed to build and gave this error:
error: ti.sysbios.BIOS: "C:/ti/bios_6_34_04_22/packages/ti/sysbios/BIOS.xs", line 209: ti.sysbios.BIOS : BIOS.cpuFreq is undefined. You must define the CPU frequency in your application configuration. For example, if the PLL is being configured for 100MHz, add this to your application configuration script: BIOS.cpuFreq.lo = 100000000;
js: "C:/ti/xdctools_3_25_02_70/packages/xdc/cfg/Main.xs", line 153: Error: Configuration failed!
gmake.exe: *** [package/cfg/Semikron_DCDC_v05_p28FP.xdl] Error 1
js: "C:/ti/xdctools_3_25_02_70/packages/xdc/tools/Cmdr.xs", line 51: Error: xdc.tools.configuro: configuration failed due to earlier errors (status = 2); 'linker.cmd' deleted.
gmake: Target `all' not remade because of errors.
When I add:
BIOS.cpuFreq.lo = 10000000;
to the cfg script, the error remains. If I change it to:
BIOS.cpuFreq = 10;
I recieve this error:
configuring Semikron_DCDC_v05.x28FP from package/cfg/Semikron_DCDC_v05_p28FP.cfg ...
js: "C:/Users/Admin/Desktop/Semikron_SYSBIOS/Semikron_SYSBIOS/Semikron_DCDC_v05.cfg", line 564: XDC runtime error: ti.sysbios.BIOS/cpuFreq: incompatible assignment: 10.0
"./package/cfg/Semikron_DCDC_v05_p28FP.cfg", line 177
gmake.exe: *** [package/cfg/Semikron_DCDC_v05_p28FP.xdl] Error 1
js: "C:/ti/xdctools_3_25_02_70/packages/xdc/tools/Cmdr.xs", line 51: Error: xdc.tools.configuro: configuration failed due to earlier errors (status = 2); 'linker.cmd' deleted.
gmake: Target `all' not remade because of errors.
I guess my questions are:
Is the above code the correct method for configuring the PLL for SYS?BIOS?
Am I doing something wrong in trying to configure the PLL through the cfg file?
