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74ls107a

Alex aan de Stegge
Prodigy 20 points
Other Parts Discussed in Thread: SN74HCS72, TLC272

Hello,

I have as design problem. I have made a design which detects a signal which compared with a reference signal which comes from an Ardino uno. The reference signal is generated by the Ardino as an block signal which is fed to a capacitor which flattens the signal to a steady voltage. By regulating the duty cycle the Ardino generates via the capacitor C5 and resistor R8 a requested voltage which is compared with the input signal (peek detector) on pin 2 of the TLLC272CDR. The design is constructed as an smith trigger and the output of the. amplifier has an positive feed back to pin 3 with resistors R9, R11 and R10.

The result of the output signal (ADC) is the blue block signal. (see attachment.) This is as expected.

The ADC signal is the input clock signal which is connected to the 74LS107AD JK-flipflop on pin 12. J and K and the inverted clear are set to high (5 Volts), so the flip-flop should toggle the output on the clock. 

But.... the output signal of the flip-flop on pin 3 responds not as expected. On the negative edge of the clock signal the output should toggle. The yellow line (see attachment) shows the produced output signal of the flip-flop. Sometimes the toggle react on the negative edge of the clock as expected.  Sometimes it doesn't react at all on the negative edge signal. Sometimes the toggle is been done on the positive edge of the clock, which should not be done.

It seems that the flipflop reacties random on the clock signal edges. I have already replaced the flip-flop chip as also the TLC272CDR. This did not help and it looks I have made an design error.

What did I wrong?

Regards,

Alex

  • 0
    Prodigy 20 points

    Think I've got it. I have used an opamp in stead of an comparator. Probably the slew rate is to slow for a good fall time of the signal. 

  • 0 in reply to Alex aan de Stegge
    TI__Guru* 96681 points

    The LS family of logic is quite old, using a type of bipolar logic. I would recommend to design with a newer CMOS based device.

    If you use the SN74HCS72, for example, connect Q\ to D, then you will have the same functionality (output toggles when CLK transitions from high to low), and you will have reduced power consumption and no limit on input slew rate. You can connect an RC to CLK\ or PRE\ to force the device to start in either the HIGH or LOW output state.

    The one down side is that the HCS72 doesn't come in PDIP for easy prototyping, but we do offer an EVM that makes it pretty easy to work with:

    https://www.ti.com/tool/14-24-LOGIC-EVM

  • 0 in reply to Emrys Maier
    Prodigy 20 points

    Thx, Emrys. Your solution forces me to redesign the PCB. I can replace the TLC272 with the comparator TLV9032DR. It has the same pin connections and is fast enough for the input of the 74LS107A.  But I keep your idea in mind for future designs. Thanks for help.