SN74LVC1G74: PRE=L CLR=L ,what will be the output Q?

Ramesh Murthy

Part Number: SN74LVC1G74
Other Parts Discussed in Thread: SN74LVC1G373, SN74LVC1G99, SN74LVC1G125, TLV803E

I need to understand the condition PRE=L, CLR=L, D=X, CLK=X. So that I can decide the logical usage of this Flipflop. Is there any timing constrain to make this state stable.

over 4 years ago

0 Ramesh Murthy over 4 years ago

Prodigy 60 points

Please provide the output Q after state 2 in below 2 image,

0 Clemens Ladisch over 4 years ago

Guru 316780 points

Table 1 (section 8.4 of the datasheet) shows that both Q and /Q will be high. This state will remain as long as both /PRE and /CLR are low.

If /PRE and /CLR go high at the same time, the output state will be random but valid.

0 Ramesh Murthy over 4 years ago in reply to Clemens Ladisch

Prodigy 60 points

please provide the output Q at state 2 of attached image

0 Rami Mooti1 over 4 years ago in reply to Ramesh Murthy

TI__Mastermind 35388 points

Ramesh,

Table 1 in section 8.4 of the datasheet provides this information.

When both PRE/ and CLR/ are low Q will be high but nonstable. This is the case for both your images. They will remain this way as long as both are held low.

Thanks,
Rami

0 Ramesh Murthy over 4 years ago in reply to Rami Mooti1

Prodigy 60 points

what is the meaning of nonstable here ?

Please help me whether the output waveform in below image are correct ?

0 Clemens Ladisch over 4 years ago in reply to Ramesh Murthy

Guru 316780 points

Yes, these waveforms are correct.

"Nonstable" means that one of the outputs will change as soon as /PRE or /CLR goes high.

0 Ramesh Murthy over 4 years ago in reply to Clemens Ladisch

Prodigy 60 points

......Thank you for the response. Please help me finding a IC with following logical truth table?

...

0 Rami Mooti1 over 4 years ago in reply to Ramesh Murthy

TI__Mastermind 35388 points

Hey Ramesh,

You can accomplish this with an XOR gate and a D-latch. You can to tie your two inputs to a 2input XOR gate and that XOR output to the LE of a d-latch such as the Sn74LVC1G373. Then connect your Input 2 into the data input of the latch.
Here's a diagram with the truth table

Thanks,
Rami

0 Ramesh Murthy over 4 years ago in reply to Rami Mooti1

Prodigy 60 points

Thank you. It seems like separate CLK raising need to be given for the state transition. But I dont have CLK option

Is there any other option to have this logic operation without CLK pulse?

0 Ramesh Murthy over 4 years ago in reply to Rami Mooti1

Prodigy 60 points

sorry i have seen wrong datasheet. Thank you for the response. Please help me to find a Logic OR gate ic with OE pin or shutdown pin?

0 Ramesh Murthy over 4 years ago in reply to Rami Mooti1

Prodigy 60 points

Please help me to find logic EX-OR IC with shutdown or enable pin

0 Clemens Ladisch over 4 years ago in reply to Ramesh Murthy

Guru 316780 points

Why do you need OE?

Anyway, you can add a buffer with OE (SN74LVC1G125), or implement the XOR with a configurable gate with OE (SN74LVC1G99).

0 Ramesh Murthy over 4 years ago in reply to Rami Mooti1

Prodigy 60 points

If both my inputs are H during power ON, then the D latch flipflop will try to maintain previous state. How to maintain output as L during power ON?

0 Clemens Ladisch over 4 years ago in reply to Ramesh Murthy

Guru 316780 points

You need to generate a low pulse at Input2 during power on. Use a reset IC (e.g., TLV803E) or a R+C circuit.

0 Ramesh Murthy over 4 years ago in reply to Clemens Ladisch

Prodigy 60 points

but RC impact will be there on each time of state transition in input 2

0 Clemens Ladisch over 4 years ago in reply to Ramesh Murthy

Guru 316780 points

Use a diode, or an AND gate.

Logic

Logic forum

SN74LVC1G74: PRE=L CLR=L ,what will be the output Q?