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VME 9U board layout guidlines.

Other Parts Discussed in Thread: SN74LVC16T245, SN74LVT16245B

Hi Team,

We are doing 9U board design, in our design Artix7 family FPGA used. FPGA to Back plan we have VME interface, that interface trace length should be around 12inch.

1) 96 pin connector to level translator  2 inch, Trace with 5.1 @ 50 ohm impedance.

2) Level translator to FPGA 10 inch trace length, Trace with 5.1 @ 50 ohm impedance.

Level translator part number: SN74LVC16T245 (16-Bit), SN74LXC8T245QPWRQ1 (8-Bit).

We are did SI simulation for VME interface. Result are given in below.

1) FPGA (LVCMOS_3V3_8mA) as driver LVT (3V3) as receiver at the time signal (transmission) quality is good (Overshoot and undershoot are with in range).

2) LVT (3V3) as driver FPGA as receiver at the time signal  quality is bad. ( we are getting Overshoot and undershoot are with in range)

The issues are listed.

1) LVT to FPGA signals transmission line required series termination. it is really required or we have any other approach?

2) VME interface Data bus is BI-Dir bus. this signals some time LVT as driver some time FPGA as driver, in this case where we can mount series termination? or we have any other approach?

3) For Data bus How we can control Overshoot and undershoot with out series termination?

Our trace length is 10 inch (max) LVT to FPGA. For this trace length who we can achieve with good signal quality, please recommend any design approach.    

Our SI simulation report is given below. please refer.

 

Case 1: Artix7 to level translator

FPGA part number: XC7A200T-1FBG676C

FPGA Buffer model: LVCMOS33_F_8_HR

Level translator part number: SN74LXC8T245QPWR

Buffer model: input_3.3V

Trace length: 10 inches

Trace width: 5 mils

Frequency: 32 MHz

  • Waveforms:

Case 3: Level translator to Artix-7

FPGA part number: XC7A200T-1FBG676C

FPGA Buffer model: LVCMOS33_F_8_HR

Level translator part number: SN74LXC8T245QPWR

Buffer model: input_3.3V

Schematic:

  

Trace length: 10 inches;

Trace width: 5 mils

Frequency: 32 MHz

Waveforms:

Case 4: With 33 ohms series termination:

 Level translator to Artix-7

FPGA part number: XC7A200T-1FBG676C

FPGA Buffer model: LVCMOS33_F_8_HR

Level translator part number: SN74LXC8T245QPWR

Buffer model: input_3.3V

Schematic:

Waveform:

Regards,

Sivakumar R

  • Hi Siva,

    I am reviewing your question and will get back to you shortly.

    Thanks,

    Sebastian Muriel 

  • Hi Siva,

    In order to maintain the best signal integrity a series termination is recommended. A series termination resistor should be placed after the FPGA. Here is one of our resources on termination techniques

     https://www.ti.com/lit/an/snla034b/snla034b.pdf?ts=1625762609632&ref_url=https%253A%252F%252Fwww.google.com%252F 

    Regards,

    Sebastian 

  • Hi Sebastian Muriel,

    VME interface control signal, Address and Data signals are single ended. please recommend series termination layout guideline.

    As per our analysis, below points are we noted in SI simulation 

    1) FPGA as driver (XC7A200T-1FBG676C drive strength is 8mA) and level translator is receiver (SN74LVC16T245). In this case we got good waveform. (Trace length is 10Inch, trace width 5.1mils)

    2) Level translator as driver (XC7A200T-1FBG676C drive strength is 24mA) and FPGA is receiver (SN74LVC16T245). In this case we have issue. we got overshoot and undershoot. (Trace length is 10Inch trace width 5.1mils). In this case we added series termination (22/33 ohm resistor) near by the LVT . VME interface data lines are Bi-DIR signals, so when we add series termination FPGA (Driver) to LVT (Receiver) rise time and fall time are increasing. LVT (Driver) to FPGA (Receiver) rise time and fall time are more increasing. 

    3) FPGA to LVT in-between we added Buffer (SN74LVT16245B). this buffer also not resolved issue.

    please share relevant trace guidelines

  • Hi Siva,

    In the waveform you posted for case 4, the overshoot improves significantly compared to case 3 without the series resistor at the output of the LVT. The overshoot cannot get much better than that so keep this in mind when designing. Regarding the increasing rise and fall times, this is the design trade-off in order to get lower overshoot and undershoot. Also, the supply voltage will fluctuate by more than that overshoot so the output cannot be guaranteed to stay under 3.3V. You must keep a 500mV tolerance on either side.

    Regards,

    Sebastian