TXB0108: IMPEDANCE REQUIREMENT FOR SINGLE ENDED NETS

GAYATRI R

Part Number: TXB0108

We are planning to use the following IC from TI:

TXB0108DQSR

SN74AVC32T245GKER
TLV320AIC12KIDBTR
LM1117IDT-3.3/NOPB
LM1117IDT-1.8/NOPB

According to convention i am aware that impedance of 50E should be maintained in the layout, for which a reference plane (supply or ground) is necessary in the stackup for all digital circuits.
However my layout engg wants to route it without a ground reference plane and says that the datasheet does not mention a 50E impedance requirement. But for SI considerations also we define impedance of 50E for all single ended nets.

Need some help here. Kindly support

Thanks and Best Regards

over 4 years ago

0 Clemens Ladisch over 4 years ago

Guru 316690 points

If you have traces where transmission line effects matter (typically, longer than about four inches), then you might want to add termination that matches the characteristic impedance of the trace. This characteristic impedance might be 50 Ω or some other value.

These devices, by themselves, do not care what characteristic impedance the traces have. (The impedance of a CMOS input is effectively infinite.) Transmission line effects are a board-level concern, so most datasheets do not talk about this. But it is described, e.g., in the section "Proper Termination of Outputs" in the LVC Designer's Guide.

So to answer your question: If you do not add termination, then the actual characteristic impedance of the trace does not matter. But if you do want to match the characteristic impedance of the trace, then you have to create a trace with a known impedance.

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TXB0108: IMPEDANCE REQUIREMENT FOR SINGLE ENDED NETS