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SN74HC541: Delay time for CL = 200pF over

Shuji Ishiwata
Mastermind 7825 points
Part Number: SN74HC541

Hi All,

I have a question about SN74HC541.
The delay times for CL = 50pF and CL = 150pF are shown in Figures 1 and 2.

Is there a formula for calculating the delay time when CL = 200pF over ?
Or is it okay to draw a graph from the delay times of CL = 50pF and CL = 150pF to derive the estimated value?

Best Regards,
Ishiwata

  • +1
    TI__Guru* 97046 points

    Hello Ishiwata-san,

    Yes, we would expect the delay to increase linearly with capacitance with only a small offset due to internal delays.

    I would recommend to use linear interpolation, or as you say, draw a graph using the existing datasheet values. This will give a safe maximum delay estimate.

    I should also note that I would not recommend exceeding the rated output capacitance of the device. This will result in increased power consumption and could reduce reliability -- we only tested the device up to 150pF.

    Usually if a larger output capacitance is required, I would recommend adding some series output resistance to reduce output current. This will also usually help with ringing at the distant end, so you end up with two benefits from one resistor.