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Logic interfacing Clarifications required

Dear Team,

I need to interface a Logic gate G1 with another Logic gate G2. Please see the figure below. As per my knowledge, the below conditions should be met.

May I know I am correct or not or missing anything.

Voh(G1)>Vih(G2)
Vol(G1)<Vil(G2)

Ioh(G1)>Iih(G2)
Iol(G1)>Iil(G2)