Gate driver up to 12V with rise/fall time 1ns

How large is the load? What propagation delay can you afford?

there is no load and the propagation delay better <10ns. (actually the faster the better)

I want to use the output of this line to generate pulse duration in order to couple on another signal. It can be considered generate FEXT on the signal line. 

Hi Aaron,

Do you have 3.3V supply gate driver with similar logic gate and rise/fall time as LMG1020 ? I only have 3.3V and 12V on my board.

Gate drivers run from the high-voltage supply.

3.3 V happens to be the high level of TTL signals. The search function has an additional column "Input threshold"; search for TTL:
www.ti.com/power-management/gate-drivers/low-side-drivers/products.html#p2869max=12;40&p598=TTL

Try the UCC27517, and measure what the actual rise/fall times are in your application.

Do you have Pspice model for LM5134B ? It has typ 3ns with 1000pF capacitance output. 

Hi, Woon,

We have a pspice model for LM5134A. The only difference between the A and B version is the logic threshold levels of the inputs.

Best regards,

Don

Hi Don,

The VIH is 2.4V(min) and VIL is 0.8V(max). Is the requirement for the minimum input pulse width ?

Hi Aaron,

For LMG1020, can both OUTH and OUTL tied together in order generate pulse width that follow IN+ ? IN- connect to GND.

Hi, Woon,

We don’t spec min pulse width for LM5134.

It is fine to tie OUTH and OUTL together on the LMG1020. 

Best regards,

Don

Ok. Thanks Don.