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TXS02612: TXS02612 schematic questions

Part Number: TXS02612

Hello,

I'm trying to do something which is perhaps a little unusual; I'm planning to multiplex SD cards, but share access between two systems with one system only seeing one SD card at a time.

To do this I've employed two TXS02612R multiplexers, with only one of the devices controlling which device accesses which card. A third analogue multiplexer controls access to the power and detect lines (schematic below). I've had success achieving a the same goal with ordinary analogue multiplexers before moving to this part.

Will this approach work with this particular part?

Are the pull-up resistors I have unnecessary due to the TXS02612R internal pull-ups?

  • Hey Craig,

    This isn't the intended application of this device and could likely have some issues. Having I/O of two different TXS devices connected adds risk for bus contention of the edge rate acceleration circuitry. You are also likely going to see some DC level issues as well. To know if this is going to work in your system, I recommend prototyping.

  • Hi Dylan, thanks for your reply.

    I assume you're refering to the note on page 4 of the datasheet...

    R1 and R2 resistor values are determined based upon the logic level applied to the A port or B port, as follows:
    R1 and R2 = 40 kΩ when a logic level low is applied to the A port or B port.
    R1 and R2 = 4 kΩ when a logic level high is applied to the A port or B port.
    R1 and R2 = 70 kΩ when the port is deselected.

    Does this mean that when the port is deselected on Mux1, the inactive IO will have a 70k pull-up resistor on them?

    Is the concern that this will interfere with the pull-up on the active port of Mux2? How would this cause DC level issues?

    Thanks,
    Craig

  • Hey Craig,

    The DC level issues I'm referring to come from the pull-ups and the Rdson of the pass FET. Whatever device is driving the I/O of the TXS device will have to sink all the current from the pull-ups (on that channel) effectively. On top of that, any current going through the pass FET will cause a voltage shift (VOL = VIL + Ipass*Rpass). 

    I expect the I/O to be loaded down with a pretty heavy capacitance as well which is not recommended as it will negatively impact the one-shots.