SN74AUP1G17: Load resistance minimum value

Paulo Monteiro

Part Number: SN74AUP1G17
Other Parts Discussed in Thread: SN74AUP1G14, , TINA-TI

Hi.

I am currently using the SN74AUP1G14 and SN74AUP1G17 Pspice models in TINA sumulations an mentioned in the attached schematic.

When, as shown in the schematic, these logic gates are loaded with 180R resistors, the attached error is produced by TINA.

Is this normal? What would be the recommended lowest load resistor for these gates?

Many thanks, Paulo BufferTestSchematic.pdf BufferTestError.pdf

over 2 years ago

0 Emrys Maier over 2 years ago

TI__Guru* 96591 points

Can you attach your tina schematic file?

0 Paulo Monteiro over 2 years ago

Prodigy 30 points

Dear Emrys, I am now including my TINA schematic. ThanksBufferTest.TSC

0 Emrys Maier over 2 years ago in reply to Paulo Monteiro

TI__Guru* 96591 points

Hey Paulo,

Thanks for sending that. I was able to find the error in the code -- it appears that the output resistance values were generated with a negative sign.

I updated the models in the attached Tina-TI file:

BufferTest_fixed models.TSC

Logic

Logic forum

SN74AUP1G17: Load resistance minimum value