SN74AUP1T97: Consequences to tying A, B, and C for Logic Buffer

Hello, I plan to use the SN74AUP1T97 as a level shifter to bring up a peripheral's logic from 1.8 to 3.3 volts to be read by my microcontroller, however I noticed that the peripheral manufacturer's design which referenced your part is using a PIN set up that is not shown in your datasheet. In their design, they have the A B and C terminals tied together. After working through this setup, I concluded that its output behavior is the same as a non-inverting buffer, which is one of the designs included in your datasheet. I prefer your datasheet's design to the one implemented by the peripheral designer because their design would require more gates to switch their states in order to accomplish the same task. I was hoping to ask if there is any reason you can think of why they would have used that alternate configuration/ if that configuration could lead to errant logic? My intuition is that their design could lead to garbage bits if there is logic changing fast enough that there could be gate propagation issues. Thank you very much in advance -Joe