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SN74LVC4245A: Question about the SN74LVC4245A behavior during Power up

Part Number: SN74LVC4245A
Other Parts Discussed in Thread: SN74LXC8T245

We are using the SN74LVC4245A for controlling 5V output logic signals and we have found an issue during power-up.

The component is configured to shift 3.3V logic signals from its side B (VCCB= 3.3V) to its side A (VCCA= 5V). The DIR pin is set to GND and the OE pin is tied to the 5V by a 4.7K resistor (as suggested into datasheet). A regulator supplies the 3.3V from the 5V. 10K resistors pull down all the outputs of the comp (side A).

  • At Power up the 5V ramps first, consequently the OE pin ramps too.
  • Second, the 3.3V starts several milliseconds after. 
  • Finally, an open collector transistor asserts the OE pin low.

This configuration work properly in many cases. Nevertheless, we have observed an issue when a residual 0.3V voltage persists on the 3.3v rail before the power up (due to a rapid power-off and power-on sequence). In this case, side A outputs are all wrongly activated and ramp with the 5V, until the 3.3V starts to ramp, and despite the pull up resistor on the OE pin.
Unfortunately, this issue create a harmful “flash” behavior on our outputs, which must remain low when powering up.

For example, see Activation of A7 below.

Could you indicate the reasons for this output activation in spite of OE pin state?
Could you suggest modification to solve this problem?

Thanks

  • Hi Benjamin,

    I'll send this over to our translation expert and he will get back as soon as he can.

  • Hi Benjamin,

    Maybe this quick power sequence leaves some residual charge making the output glitch during power up. During the power up sequence its possible for the device to have some internal race conditions that could lead to glitching. Adjusting the ramp rate may be able to fix this, but switching to another device that is p2p may be the best option. What package are you using?

  • Hi Dylan,

    We use the package TSSOP24 with the part number SN74LVC4245APWR.

    So as to avoid confusion,
    We haven’t problem when the power-up sequence is quick.
    But when the power-up is slow (1V/ms or less), the output port A switches ON (harmful “flash”).

    We want to understand this behavior so as not to modify our equipment.

    Thanks

  • Hey Benjamin,

    This has to do with internal nodes not being powered and other voltages potentially coupling causing this glitch like behavior. If you want a robust power up I'd recommend the SN74LXC8T245 device. Its p2p so you can just drop it in. It has glitch suppression circuitry that eliminates any possible glitching during any type of power sequence. On top of that, you also will get other parametric benefits.