Hi team,
My customer use TXS0102 in their project, but they met below issue, could you please help give some suggestions?
Thank you.
The customer found that the SDA signal of I2C has a problem of keeping low level for a long time on the B side of txs0102.
The I2C interface is an OD gate structure with a rate of 100Khz.
1. The customer uses TXS0102 on the i2c bus, and the connection topology: CPU---I2C-----TXS0102-----I2C----SPD(eeprom);
2.The problem is that CPU-side I2C while writing to the EEPROM, the shave releases the SDA signal after an ACK reply from slave(EEPROM), but the actual test found that the txs0102's B2 was always low. As a result, the timing does not have the next start process, and the subsequent timing is out of order.
As shown in Figure 1 below, the results of the test on the B-side of the TXS0102 show that the i2c_sda should be pulled high after the EEPROM releases i2c with the arrow in Figure 1, but the actual test waveform is not pulled high. This results in the i2c timing missing a start process.
As shown in Figure 2 below, the results of the test on the TXS0102 A side, the same finding was that the i2c_sda on the A side should be pulled high after the EEPROM release i2c by the arrows in Figure2, but the actual test waveform was not pulled high. Although the wave has a protrusion, However, the entire i2c_sda level is low because B2 is pulled low all the time.
Figure1
Figure 2
Could you please help analyze why txs0102 behaves abnormally with the i2c signal pulled, what triggers are causing it?
Thank you very much.
Regards,
ivy
