Other Parts Discussed in Thread: SN74LV8154, PCM1794A
I built an entirely discrete logic based circuit and I have this shift register converting data from the Y bus on an SN74LV8154 to serial data and my logic design allows the shift register to load 1 extra bit so it ends on the value of the SER input (which is held low) before SH/LD goes low again but the output ends up in a seemingly random state not related to the input where it could be high or low and if it's high the output will slowly die down while oscillating at a high frequency well above the 10MHz clock source.
I have 4 of the counters in series with RCOA of one connected to the clock A input of the next which counts correctly, the clock source is a 10MHz OCXO and the rest of the project gets the clock from a decade counter and runs at 1MHz which despite the low duty cycle seems to work OK.
The problem may have something to do with the 3 state output of the counters since the output seems to fall off slowly, I could add an AND gate to the output of each shift register as a workaround but I'd have to order more and I can't fit more on my project board as it is so I'm posting here to see if there's anything else I could do.
You can see how the circuit is expected to work with the Falstad circuit simulator: https://tinyurl.com/y48e6lsl
The counters don't roll over in the simulation simply so I can see if it outputs the data correctly, the 4 counters and latches make the SN74LV8154 counters, they are then connected to the shift registers.
I'm only simulating the first 8 bits of the counters just to simplify it but you can see the register selection states.
Click the Serial In pin H for at least 1 clock cycle to trigger it
Here is a picture of my project
The SOT-23 by the OCXO is a 3.3v to 5v level shifter, see if you can make sense of the rest.
Here you can see 2 samples of the output where at each 10th microsecond is the serial stop bit followed by 8 data bits then a 1 clock pause before the next byte of data and as you can see due to the way the shift registers are connected via a NOR gate, if the output of 1 more more remains in the high state the data after it is blocked.
This is the serial clock, the overshoot is mostly due to the scope probe ground lead:
Here you can see the oscillation which happens only if the shift register output QH remains in the high state, its about 37MHz:
Here you can see the same QH output as above but when the serial data is transmitted, keeping in mind it will remain in a random state when SH/LD goes low:
I hope that's sufficient data ; )
