SN74AXCH2T45: BUS-Hold latch delay time and BUS-hold release condition

Shuai Yuan

Part Number: SN74AXCH2T45
Other Parts Discussed in Thread: SN74AXC2T45

Lenovo customer uses SN74AXCH2T45 replace SN74AXC2T45, and there is one more spec for bus-hold latch with SN74AXCH2T45. Now we have a question that is: what is the delay time when bus-hold latch occurs and what's the release condition to latch off BUS-hold?

over 3 years ago

0 Clemens Ladisch over 3 years ago

Guru 318700 points

The bus-hold latch is always active. It has a very high output impedance (about 5 kΩ) to allow the actual input signal to override it.

See section 5 of System Considerations For Using Bus-hold Circuits To Avoid Floating Inputs.

0 Shuai Yuan over 3 years ago in reply to Clemens Ladisch

TI__Intellectual 2290 points

Thanks for your reply and technical support. Could I please know how the stability and accuracy behavior with the output impedance(5 kΩ)

0 Clemens Ladisch over 3 years ago in reply to Shuai Yuan

Guru 318700 points

The datasheet specifies this as the maximum hold current (I_BHx) and the minimum overdrive current (I_BHxO); the actual possible output current is somewhere between these values.

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SN74AXCH2T45: BUS-Hold latch delay time and BUS-hold release condition