This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74AUC08: compatibility with clock signals

Part Number: SN74AUC08

Hi Team, 

Looking for a low latency device to isolate clock signals from a CPU board to a Line Card. (dip switch like device that can isolate the incoming clocks while the line card is not turned on)

 

Does the SN74AUC08 handle hot-plug? What would be the behavior of the part if it received a live clock input with no VDD power applied? Is the part at risk of being damaged? Will the clock cause the VDD to have a pre-bias?

Is this handled by the Ioff feature?

Thank you, 
Delaney

  • Hi Delaney,

    Is this handled by the Ioff feature?

    The Ioff feature prevents back-flow when the supply of the device is 0V and the output has a signal applied to it from an active bus.

    Does the SN74AUC08 handle hot-plug?

    This device is what we call "Level 1" isolated for partial power down applications, which means it can be powered down and disconnected from a circuit, or connected and powered up without causing damage to the device itself -- assuming proper design of the system. There's an application report that discusses the levels of live insertion in detail here: https://www.ti.com/lit/an/scea026/scea026.pdf 

    Regarding the other 2 levels mentioned in the linked app note:

    Power-up 3-state might be useful for this application, however I don't know of any AND gates that include that feature -- it's limited to bus buffers, and only those that operate above 2.7V for the most part. Probably not an issue to be concerned with though.

    When the device is powered off, it sounds like the data will be at the input only, so Vcc bias won't make a difference here -- that only applies when the output is connecting to an active data bus.

    What would be the behavior of the part if it received a live clock input with no VDD power applied?

    Without power applied the part won't do anything. The input and output will be high impedance as defined by the Ioff spec.

    Is the part at risk of being damaged?

    Yes, but not from normal signals. Usually damage occurs from a lack ESD protection or from incorrect design of the connectors that can lead to large mismatches in VDD GND  and signal lines prior to a complete connection being made.

    Will the clock cause the VDD to have a pre-bias?

    Not 100% sure of your meaning here -- if you're asking if the supply will be back-powered by the input signal, then no -- this device does not include positive clamp diodes so there is no path for current from the input to the supply.

  • Hi Emrys, 

    Thank you for the response!

    Quick follow up:

    VDD = GND

    GND = GND

    Signal line = 3.3V

    The connectors between the boards are fully mated.

    Does this constitute a “large mismatch”?

    Thank you, 
    Delaney

  • No; the absolute maximum ratings allow 3.3 V.

  • Perfect, thanks Clemens! Looks like this part might work then!

    Best,

    Delaney