TXU0304-Q1: Why could we use 200Mbps data rate @ 3.3V to 5.5V level shifting in spite of signal propagation delay = 0.5~10ns?

There are several buffer stages. You can apply a new voltage at the input even while the output has not yet finished (dis)charging the load.

Hi Ladisch, 

Sorry I cannot understand what you mention. Could you please explain with some waveforms and schematic for my understanding?

Regards,
Ochi

The internals looks something like this:

Hi team, 

Does higher propagation delay than 1/2 * SPICLK period lead communication error? Please take a look at lower figure. I guess it leads out od sync between Master In Slave Out" and "SPICLK" by using level shifter. 

Why could we use 200Mbps data rate @ 3.3V to 5.5V level shifting in spite of signal propagation delay = 0.5~10ns? SPI master output clock is 200MHz (come from 200Mbps), which is equal to 5ns a period. However, TXU0304-Q1 has 0.5ns~10ns propagation delay for 5.0V to 3.3V transition @TA=125C shown in "7.11 switching characteristics VCCA=3.3+- 0.3." It leads propagation delay > clock period and looks no correct operation. 

Regards,
Ochi

Signals going in the same direction will have similar propagation delays.

But the MISO signal indeed will be delayed by two translations, so the worst-case delay could be 20 ns.

LVC translators like the SN74LVC2T45 have a worst-case t_pd of 4.4 ns, but that is still too much.

What devices are you using? Would it be possible to use LVDS?