Hello,
in the datasheet of the TXS02612 level translator, a power sequence is given which "should be followed". Can you explain what may happen if the sequence is not exactly followed, e.g. if VCCB ramps shortly before VCCA? Are the mentioned consequences (excessive supply current, bus contention, oscillations, ...) only observed during the bad sequence condition or may they even persist once both voltages VCCA and VCCB have reached steady state?
Is it acceptable if both, VCCA and VCCB, ramp simultaneously?
Implementing a strict power-up sequence (B after A=steady state) would result in additional circuitry for our application, while some additional supply current during start-up may be acceptable.
Thank you!
