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SN74LVC112A: Alternative with Lower Drive Strength?

Darren (FAE)
Expert 5483 points

Part Number: SN74LVC112A

I need an alternative to the "LVC" logic family "112A" Dual FF device.
There is some Overshoot we need to limit - a lower drive strength P2P device should solve the issue without requiring PCB changes.

I am looking at the CD74HC112 as a candidate...could you confirm?
*Required Package is TSSOP

VOH

Vcc-0.5V(@1μA)
I believe this is a typo...VOH needs to be within Vcc - 0.5V over the rated output drive current (4mA?)

VOL

0.5V(@1μA)

Again, a typo...VOL means sinking current through the internal FET; thus a voltage drop...should be less than 0V + 0.5V for rated current (4mA?)

Output tr/tf

<5ns

*Larger than the LVC112A device

This is a little confusing, but I understand they need an output rise/fall time of "greater" than 5ns.

Propagation Delay

<15ns difference between tPHL and tPLH

The datasheet doesn't spec skew between tPHL and tPLH; it only specs the "Typ" propagation delay. Do we have any data comparing the TYP tPHL vs TYP tPLH? Are they within 15ns of each other (at 3.3V?)

Clock Input (VIH)

0.9Vcc

Clock Input (VIL)

0.1Vcc
  • 0
    Guru 317750 points

    This is the only other '112 device in the TSSOP package. And HC indeed has much lower drive strength.

    1 µA is appropriate for a high-impedance CMOS input; the rated output current is not actually needed.

    Rise/fall time depends greatly on the capacitive load. (The HC test condition is 15 pF; the LVC test condition, 50 pF.)

    Skew is not specified. But CMOS outputs are designed to be symmetrical; I'd expect the typical value to be < 1 ns.

  • 0 in reply to Clemens Ladisch
    TI__Expert 5483 points

    Hi Clemens,

    Appreciate the reply. Quick follow-up:

    DS shows device can handle 25MHz at 4.5V or greater. Can 25MHz be achieved at 3.3V? (It looks like maybe TYP can achieve 25MHz, but not over temp?)

  • 0 in reply to Darren (FAE)
    Guru 317750 points

    Yes. With linear interpolation, the maximum propagation delay at 5 V can be estimated as 33.3 ns, and at 3.3 V, 103 ns. Applying the same factor to 60 MHz estimates the maximum frequency at 3.3 V at about 19 MHz.