Dear,
the datasheet Note 2: When Vcc = 2V, Tt =1000nS =1000nS /V x (1.5V-0.5V) ? If Vcc=4.5V, Tt= 500nS/V x (3.15-1.35)=900ns, the chip will not be damaged. As long as it is below 1.35V or above 3.15V, it is safe?
If not, please help to explain, thank you very much ~
Is there a reference value for Vcc=5V?
Dear ,
1.you said ''Transition time is measured from 10% to 90%.' , i am confused， the datasheet is referred to the threshold from VIL max to VIH min , for example， Vcc-4.5V, but 10%~90% is 0.45V~4.05V, however ， VIL max to VIH MIN is 1.35V~3.15V as datasheet, so Which one should I take as the standard ？
2. CD74HC165 datasheet is referred to 10% ~90%
Hi Cooper,
1.you said ''Transition time is measured from 10% to 90%.' , i am confused， the datasheet is referred to the threshold from VIL max to VIH min , for example， Vcc-4.5V, but 10%~90% is 0.45V~4.05V, however ， VIL max to VIH MIN is 1.35V~3.15V as datasheet, so Which one should I take as the standard ？
Everything that I've said and the datasheet says are in agreement here.
I don't see anywhere in the datasheet where it claims the transition time was measured from VIL to VIH. It does state that you should not have the input between VIL and VIH for an extended time, which is correct.
It also clearly defines the measurements for rise and fall time, which can also be referred to as transition time, as 10% to 90% in the PMI section:
Dear Emrys Maler
Thank you very much，actually，we already switched to 74hcs165, however, there are some problems during the application of 74HCS165.
Our apllication is shown as below
Almost 50 74hc165 chips are applied in 16 logic card of one chassise sharing the same control sigals (CLK /LD ) from the CPU based card throu gh the backplane.
However, there always some bits are not correctly transmited to CPU card when using the 74hcs165, we alreay checked that the inputs are stable logic , and the tr time for clk is about 400ns-1us with different configration. When we replaced the 74hcs165 with cd74hc165, the transmition is very good without any mistakes, but the tr/tt time can not meet the requiremens of cd74hc165. The mistakes will be worse during the Radiate Susceptibility test aroud the 100M frequcey for 74hcs165. That's why we very care about the tr/tt time.
Q1: Are there any problem in our application scheme?
Q2: We believe that the 74hcs165 has better performance for the slow tt/tr time, but why there is no transmition mistakes in 74hc165 even the tr/tt time are not meeting the requirements of datasheet?
Looking forward you reply!
Many Thanks!
Chen Yinjie
I expect that connecting 50 devices directly to your processor will overload it. Most modern processors are designed to handle relatively light loads (20pF), and each device adds 5pF -- plus the trace capacitance to the device. Additionally, I expect that the distance between registers is relatively large based on your description. This can cause mismatches in clock and data timing that can result in lost data. It sounds like you're getting lucky with the CD74HC165 working and it may not work under all circumstances (across temp / process corners)
This graphic shows how data can be lost if the clock arrives in the wrong order:
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In order to ensure that no data is lost due to timing, the clock should always arrive at the last device in the chain first and propagate towards the first device. The following graphic shows the appropriate method to avoid data loss:
