SN74LVC126A: what if I tie outputs of two SN74LVC126A buffers together and drive high / low respectively

There is no current clampig feature. The resistances of both outputs add up, so the current will be about half that of a short, which is still enough to damage them.

Why aren't you using a single buffer with appropriate logic to control its output?

Thanks. The diagram was simplified.

In fact the two buffers in the diagram are on two identical nodes, with one on each. The outputs are wire-AND'ed on the mid-plane to control a shared device on a 3rd board.

Do you have recommendation of other tri-state IO buffer / driver for my application? i.e. tolerate the bus conflict and not damaging?

There aren't any logic devices that are designed to do this -- just add a series resistor to prevent damage.

What current, at what voltage, do you need?

I'll need a 3.3V tri-state IO, capable of up to 20mA driving strength.

Use four LVC outputs in parallel, with a 75 Ω series resistor at each pin. The effective resistance when driving the load in the normal case is about 19 Ω, which is near the output impedance of a normal LVC output, with a voltage drop of about 0.4 V. During a failure, the current is 22 mA per pin, or 88 mA in total, which is inside the absolute maximum ratings.

If you need a smaller voltage drop, use eight-channels devices like the SN74LVC541A.