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SN74AVC16T245: B port pull hign behavior when the VCCB is powered on

Fanbin Meng
Expert 8705 points
Part Number: SN74AVC16T245
Other Parts Discussed in Thread: SN74AXC8T245

Hi team,

the customer report an issue and want to check with you if it is a normal behavior:

During the VCCB is powered up, the B port signal(marked in the red square) is pull high first and then pull low.

  • 0
    TI__Mastermind 45725 points

    Hey Fanbin,

    Yes, power up glitching can be expected due to internal race conditions and floating nodes as the supplies ramp. If this is a problem for the customers system, I recommend using two SN74AXC8T245 devices instead - these devices have glitch suppression circuitry to eliminate these glitches.

  • 0 in reply to Dylan Hubbard
    TI__Expert 8705 points

    Hi Dylan,

    Thanks for the reply!

    1. first, the customer want to know more details about the internal race conditions and floating nodes, can you provide a details reasons discription about how is the glitches occur?

    2.i think the gliches issue occurs when the time sequence between the pull up power and IO output.

    the current setting is OE and portA is already ready and the  portB is used as the output, the VCCB is start to ramp up. when the VCCB is not eatablished, the portB io is the high depandence status, when there is a IO pull up voltage there, the IO voltage start to ramp up a little bit, and when the VCCB is fully established and the IC is start to working normally, the port B become logic low(the input A port is low)

    is this the right explanation for this case? if yes, can the SN74AXC8T245 used to solve this issue?

  • 0 in reply to Fanbin Meng
    TI__Mastermind 45725 points

    Hey Fanbin,

    Its a little hard to see all that with the limited info provided originally, but that is a reasonable explanation. If VCCB is at 0V then the VCC isolation/Ioff circuitry will put the I/O into a hi-z state and will be pulled up if there is a pull-up connected to it. Once the B port is supplied enough and set as the output, it can then pull the line Low if the A input is Low.

    The glitch I mentioned is a scenario when both supplies are ramping typically at the same time. The control circuitry can get confused in a sense which can lead to glitches on the I/O. This can be eliminated with the SN74AXC8T245, but the scenario mentioned above would still happen with this device.

  • 0 in reply to Dylan Hubbard
    TI__Expert 8705 points

    Thanks Dylan,

    and is there any possible solution to avoid the scenario mentioned above

    because for customer's system, the downstream load can't accept this 

  • 0 in reply to Fanbin Meng
    TI__Mastermind 45725 points

    Hey Fanbin,

    Can they not just remove the pull-up or switch it to a pull-down?

  • 0 in reply to Dylan Hubbard
    TI__Expert 8705 points

    I'm sorry Dylan,

    could you describe it a little clearly? i'm not sure how we suggest the customer to change their design.

    can you mark it in the shcematic picture i showed you? or is there any other informantion we need to help better locate the root cause?

  • 0 in reply to Fanbin Meng
    TI__Mastermind 45725 points

    Fanbin,

    You mentioned the I/O being pulled up and there are pull-ups in the schematic from what I can see. So if they don't want them to pull-up the voltage they can either remove them, or make them pull-downs instead to see if that fixes the issue.

  • 0 in reply to Dylan Hubbard
    TI__Expert 8705 points

    Thanks Dylan,

    if they remove the pull up, is  the IO driver strong enough?

    what is our IO internal structure, don't we need the extra pull up in current design?

  • 0 in reply to Fanbin Meng
    TI__Mastermind 45725 points

    Fanbin,

    What exactly is the purpose of the pull-up? It sounds like it is causing the system issues more than anything else. This translator doesn't need pull-ups to drive High.