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SN74AXC8T245: RGMII Bus

Hielke Bakker
Prodigy 70 points
Part Number: SN74AXC8T245
Other Parts Discussed in Thread: SN74AVC16T245, SN74AVC8T245

We are using a 1.5V MAC that needs to be connected to a 3V3 PHY via a RGMII bus. We are planning to have a 1000Mbit/s connection via this RGMII interface.

We want to use the SN74AXC8T245 for this.

  • Is the SN74AXC8T245 fast enough;
  • Is the timing (delay) of the SN74AXC8T245 with in the specs for a RGMII Bus?

Thanks for your help.

  • 0
    TI__Mastermind 45635 points

    Hi Hielke,

    This device isn't specified for RGMII so it will take some effort on your end to verify if it will work in your system. This device works at those voltages and should have a data rate of ~380 Mbps (per channel) with that configuration. All the timing related specs for your reference are located in section 6.10 of the data sheet.

  • 0 in reply to Dylan Hubbard
    Prodigy 70 points

    Thanks, for your reply,

    I had a look at the timing there is not a lot of margin between the RGMII specification and the timing characteristic of the SN74AXC8T245.

    If we would use a 100Mbit connection via the RGMII bus, the clock would drop to 25Mhz and the data rate would also drop. Is the SN74AXC8T245 better suited for this speeds/timing?

    Do you know of customers that have implemented the chip in RGMII level shifting applications?

    Are there any level shifter that are specified for RGMII level shifting?

  • 0 in reply to Hielke Bakker
    Prodigy 70 points

    Are there any level shifter that are specified for RGMII level shifting?

    the SN74AVC16T245? 

  • 0 in reply to Hielke Bakker
    TI__Mastermind 45635 points

    Hi Hielki,

    The SN74AXC8T245 is still fairly new so I haven't really seen proof of other customers using it. However, I have seen customers use the previous generation SN74AVC8T245 for 1.8 V to 3.3 which is pretty much equivalent to your scenario. When asked these are the two devices I recommend. The 16 channel version could also be a candidate, but I think 8 ch is typically chosen for flexibility in routing.

    I would have more confidence in the 100Mbit operation mainly due to how strict the timing requirements are for 1000Mbit. In my opinion, it doesn't seem like they spec'd that protocol with the intention of have some interfacing device between the MAC and PHY (very little margin) especially with how critical even the layout routing is.

    In the future, this is a gap we would like to close with a translator so if there is a next generation to this system I recommend coming back to see if we have a better solution that we can guarantee operation for 1000Mbit.