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SN74AXC4T774: Level Translation with Multi-Slave SPI

Viktor Schneigelberger
Intellectual 1200 points
Part Number: SN74AXC4T774
Other Parts Discussed in Thread: SN74HCS151

Hello Team,

Could you please help with the following question regarding the use case of SN74AXC4T774 as level translator together with 2 SPI slaves as described in the app note SCEA065B figure 2-2?

The issue is on MISO side because it appears that when SPI slave MISO has its output Hi-Z, the output of the SN74AXC4T774RSVR A3 (U4001) is not set Hi-Z but Low level. So when the second SPI A4 pin (U8501) slave send a High level, the signal is short-circuited to the low level between both level translator A3 (U4001) and A4 pin (U8501).

So we think that the suggested architecture in figure 2-2 might not work.

Maybe 2 solutions:

  • Solution 1: Connect the #OE signal to SPI Slave Chip Select -> in this case when the device is not selected MISO output (in level translator point of view) is Hi-Z
  • Solution 2: group together all MISO signal from Slave (as they have the same potential) and connect them to a unique input of a level translator -> In this case the Hi-Z state and short between MISO will not appear

What do you suggest? Do you have an alternate solution?

Regards,

Viktor

  • +1
    Guru 318620 points

    Yes; figure 2-2 is wrong.

    Both of your solutions would work. (All signals that might be disabled need a pull-up/-down resistor to prevent them from floating.)

    It would be possible to disable only the MISO signal(s) with 74xx125 buffers. Combining the MISO signals with a multiplexer like the SN74HCS151 is probably overkill.