SN74AHCT08: About delay

Liu Yang

Expert 6185 points

Part Number: SN74AHCT08

Hi Team,

If I use SN74AHCT08PWR as a buffer for high speed serial signals of 50 MHz (about 27 ns per bit), is there any problem?

If the high speed signal is inputted to the SN74AHCT08PWR, does the signal fail by the delay?

Beat Regards,
Tom Liu

over 2 years ago

+1 Clemens Ladisch over 2 years ago

Guru 282680 points

The worst-case propagation delay is 9 ns.

+1 Owen Westfall over 2 years ago

TI__Expert 8871 points

Hi Liu,

Below is the switching characteristics on the data sheet.

As Clemens said the max prop delay will be 9 ns so you should be fine for this signal.

Regards,

Owen

0 Liu Yang over 2 years ago in reply to Owen Westfall

TI__Expert 6185 points

Hi Clemens and Owen,

Thank you for your answer and I knew 9 ns is fine for my signal.

I have another question:

If the high speed signal is inputted to the SN74AHCT08PWR, does the signal fail by the delay?

Beat Regards,
Tom Liu

0 Clemens Ladisch over 2 years ago in reply to Liu Yang

Guru 282680 points

Sorry, what do you mean with "fail"?

0 Liu Yang over 2 years ago in reply to Clemens Ladisch

TI__Expert 6185 points

for "fail" I mean is there any problem in the signal, or how will the signal be affected.

+1 Clemens Ladisch over 2 years ago in reply to Liu Yang

Guru 282680 points

When the input signal changes, the output signal changes (after the propagation delay). There is no intermediate state.

The speed of the rising/falling edges depends on the load capacitance. For digital signals, these details usually do not matter, but if you care, you can use the IBIS model to simulate the waveforms (or measure the actual device).

Because of the holidays, TI E2E™ design support forum responses will be delayed from Dec. 25 through Jan. 2. Thank you for your patience.

Logic

Logic forum

SN74AHCT08: About delay