SN74AHC1G08: AND gate SN74AHC1G08 & D Latch states

Anand Meharwade

Part Number: SN74AHC1G08
Other Parts Discussed in Thread: SN74ALVCH373, SN74HCS72

Hello,

I have three queries:

1. I would like to know what would be the output state (shorted to VCC or GND or Hi-Z) of the AND gate SN74AHC1G08 when the IC get damaged/failed due to any reason (e.g. due to over voltage, ageing, temperature etc.).

2. In the SN74ALVCH373 D latch truth table, with OE = High, the Q becomes High Z. What happen if the Q is pulled to High with 3.3V using pull up resistor. does it stay High?

3. Please confirm my understanding for D latch as per truth table in page 2 of datasheet (SN74ALVCH373).

a. when D = LOW and LE transition from High to Low, then Q stays at LOW irrespective of change in the state of D input

b. When LE = HIGH, the input at D flows to Q

let me know if any clarifications required. Thanks for the support in advance.

Regards,

Anand M

over 2 years ago

0 Clemens Ladisch over 2 years ago

Guru 281410 points

1. Damage is unpredictable. Any input or output could be partially or fully shorted to anywhere else.

2. As long as the pull-up resistor is connected, it will continue to pull the line high.

3. Yes.

0 Anand Meharwade over 2 years ago in reply to Clemens Ladisch

Expert 1090 points

Dear Clemens Ladisch,

Thanks for the response and clarification, for 1st query. which would be case of the higher probability.

Regards,

Anand M

0 Clemens Ladisch over 2 years ago in reply to Anand Meharwade

Guru 281410 points

This depends greatly on the surrounding circuit. In general, pins that see overvoltage break first.

0 Anand Meharwade over 2 years ago in reply to Clemens Ladisch

Expert 1090 points

Dear Clemens Ladisch,

Thanks for the info. One last question, for D latch, the output latches on transition of LE pin from High to Low, But I have requirement of Latching circuit when D pin goes high to low and stay at low until the MCU resets it. Could you please recommend the device for this logic?

Thanks for the support and appreciate your timely response.

Regards,

Anand M

+1 Clemens Ladisch over 2 years ago in reply to Anand Meharwade

Guru 281410 points

Use a D-type negative-edge-triggered flip-flop (e.g., SN74HCS72), connect the input signal to /CLK, connect D to GND, /CLR to V_CC, and initialize/reset it with /PRE.

+1 Owen Westfall over 2 years ago

TI__Expert 8591 points

Hi Anand,

I would go with Clemens suggestion the only thing that I'll add is to double check parameters like supply voltages and drive strength before ordering that specific part because the SN74ALVCH373 has a bus-hold, can go down to 1.65 V and has much higher drive strength than the proposed SN74HCS72.The SN74ALVCH374 is the closest you can get, but it is positive edge triggered, so unless your parameters aren't flexible I would go with SN74HCS72.

If you have any more questions feel free to ask.

Regards,

Owen

0 Anand Meharwade over 2 years ago in reply to Owen Westfall

Expert 1090 points

Thanks Owen and Clemens Ladisch for the support & clarification in this regards. I would go with SN74HCS72 which meets my requirement.

Thanks

Anand M

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SN74AHC1G08: AND gate SN74AHC1G08 & D Latch states