Other Parts Discussed in Thread: DP83867IR, 2N7001T, TXU0101
Hi,
I am using the TXS0102 device on the MDIO interface between Xilinx SOC device and the TI DP83867 Phy device (Phy device located on external board connected via 1.5 feet cable).
For the MDIO data signal, I have a 2.2K external pull up close to TI DP83867 Phy device as per device datasheet recommendation. For the MDC clock signal, I do not have external pull ups (TXS0102 has 10k internal pull ups)
The Xilinx SOC device MDIO interface has Push pull output.
I have a few questions:
- I observe a drooping waveform (droop from 3.3V to 2.3V) for the MDC clock high level at the TXS0102 A output
The input waveform is clean.
- Can you please help advise what is causing this droop and if it can be corrected?
For reference the MDIO output waveform is clean:
2. Is there a specification for Overshoot/ Undershoot at the TXS0102 input pins?
I could not find this information in the TXS0102 datasheet. Or can I consider the section 6.1 Absolute maximum ratings of minimum -0.5V and maximum VCC +0.5V as the spec?
3. There is an overshoot of 3.63V at the TXS0102 Clock MDC:
I guess this is caused by the PMOS transistors turning on for short duration during the transition. I am considering if I should include a series resistor at TXS0102 output to damp this overshoot. Please advise if you see concerns with this.
Thanks
Louis