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SN74GTL2003: Level translator

Part Number: SN74GTL2003
Other Parts Discussed in Thread: TXU0304

Hi team,

I have used this SN74GTL2003PW level translator in my design on a JTAG interface and found out that the JTAG link is very unstable. Below is my circuit diagram.

I have a few queries regarding this level translator. Please suggest

1) Do I need to have a Decap on SREF pin? is it mandatory for the proper functioning of the level translator? what happens if I do not place a Decap on SREF pin?

2) Is there a requirement for this level translator to have DREF side voltage higher than SREF side? or anything is fine like I can have SREF voltage higher than DREF side

3) Do I need to have pull-ups on SREF side also for the proper functioning of this device? or just the DREF side pull-ups fine?