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SN74LVC1G126: Glitch at SN74LVC1G126 output on power up

Louis Sankoorikal
Expert 2345 points
Part Number: SN74LVC1G126
Other Parts Discussed in Thread: TPS3808, TLV803E

Hi,

We are using the SN74LVC1G126YZPR in our design. We are observing an unexpected glitch on the SN74LVC1G126 output on Power up which is impacting our board as it triggers a power cycle.

We were expecting the the output to be in High Impedance state on power up. However we observe that on power up, the SN74LVC1G126 pulls the output low for around 50useconds.

As per SN74LVC1G126 datasheet " To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor;"

We have connected the OE pin to 1K pull down resistor on power up. It is also connected to TI 74LVC1G74DC flipflop Q output. The 74LVC1G74DC output rises to around 220mV on power up. 

 The SN74LVC1G126 is connected to a TPS3808 MR reset input which triggers power cycle. Hence we want to avoid glitch on the SN74LVC1G126 on power up.

  • Please advise if there is some way to avoid this glitch on the SN74LVC1G126 on power up.

I have attached the schematic circuit and the waveforms at SN74LVC1G126 Y output, VCC and OE on power up. (Note in the waveform the Y output is labelled MR (Manual Reset))

Thanks

Louis

  • 0
    TI__Guru* 96591 points

    Hi Louis,

    It looks like the output is turning on slightly from the OE pin increasing by ~100 - 200mV. It's only drawing about 40uA (note that the blue line does not reach 0V and only goes down to 1V).

    Can the 100k pull-up be changed to a 10k pull-up? I expect this would solve the issue -- the same 'glitch' will occur - but the pull-down should be much weaker than the pull-up.

    The root cause is likely that the DFF (LVC1G74) is starting up in the 'high' state at the output before the reset is able to force it into the 'low' state. This all happens well below the operating voltage of the devices.

  • 0 in reply to Emrys Maier
    Expert 2345 points

    Hi,

    We tried reducing the 100K to 1K. However we still see glitch on the SN74LVC1G126 output. It drops to 1.58V which is below the VIH threshold of the TPS3808 MR input of 0.7 * VDD (3.5V)

     

    It seems the SN74LVC1G126 is pulling the ouput low with a quite low resistance. From the measured voltage values with 1K pull and trying to calculate the SN74LVC1G126 output internal pull down resistance, considering Voltage divider from 5V, it appears that the SN74LVC1G126 output internal pull down resistance is around 462 ohms.

    I need to reduce the pull up resistance to around 180ohms to ensure the SN74LVC1G126 output is above the VIH min (3.5V (0.3*VDD)) of the TPS3808 MR input.

    In this case the TPS3808 sink current would be around 28mA which is quite high and also requires high power rating for the 180 ohm pull up resistor.

    Please advise if there could be any other solution.

    Thanks

    Louis

  • 0 in reply to Louis Sankoorikal
    Guru 243120 points

    The problem is that the OE input does not stay at GND (which is caused by the flip-flop not having an /OE input). Workarounds at the output are unlikely to help.

    Add a reset IC like the TLV803E to force OE low during power up, make R3357 weaker, and add a series resistor at the Q output so that the reset IC can override the flip-flop.

    Is it really necessary to have the flip-flop? Can't you drive the OE directly from a GPIO?