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SN74AVC16T245: Data rate confirm

Part Number: SN74AVC16T245
Other Parts Discussed in Thread: DS90LV011A, DS15BR400, SN74AVC2T245, SN74LVC8T245, SN74LVC16T245, TXU0204, SN74LXC2T45

Hi,

I am going to tanslate a 200Mbps signal from 1.8V to 3.3V. The SN74AVC16T245 maximum data rate is 380Mbps for 1.8V to 3.3V level- shifting in the datasheet. but i aslo see the maximum tPLH and tPHL in switching caractersitics is 3.3ns. Does it mean the worst data rate is only 151Mbps (1/(3.3ns+3.3ns))? if i wish to tansfer the 200Mbps signal stably. what model may i use?

Regards,
Shu

  • When you add up tPLH and tPHL, the unit of the result is MHz. 1 / 3.3 ns = 303 Mbps.

    Anyway, using the propagation delay gives you only a pessimistic estimate. The internal circuit is a little bit pipelined; you can apply a new voltage at the input buffer even when the output buffer has not yet finished switching.

  • Sorry, i made a mistake. our signal is 200MHz, 400Mbps. i need 1.8V transfer to 3.3V. I didn't find chip has such high transfer speed. we hope the chip can transfer 400Mbps date with maximum rise and fall time.

    Regards,
    Shu

  • The datasheet says 380 Mbps because the guaranteed maximum is 380 Mbps. 400 Mbps is not guaranteed.

    There are LVDS transceivers that can handle 400 Mbps. Is it really necessary to use single-ended signals?

  • Actually, we will connect this level translator to a LVDS driver to drive 400Mbps LVDS signal. The LVDS driver model is DS90LV047 with 3.3V LVCOMS input. Our controller output voltage level is 1.8V. That is why I am looking for a 400Mbps translator.

    Another way is to make our controller to output LVDS signal, then use a fast LVDS->LVDS driver to transfer the signals to the load. But we have 48 pairs LVDS signals. That will occupy too much I/O of the controller. And I only find DS90LV011A which is a single channel driver. So I have to use 48 chips on my board.

    So is there a faster level translator or multi-channel LVDS driver?

  • There are multichannel LVDS buffers like the DS90LV084 or DS15BR400/1.

    Outputting LVDS from the controller is preferred. But you can also use an LVDS input for single-ended signals; see How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver.

  • Thank you very much!

    The LVDS driver may be my best solution. i shall abandon the level translator because the limited data rate.

    Regards,
    Shu

  • Hi Wang,

    In addition, please also note that SN74AVC2T245 is specified for up to 500 Mbps (250MHz) for 1.8V to 3.3V translation, thanks.

    Best Regards,

    Michael.

  • Hi Michael,

    I saw the SN74AVC2T245 minimum tPHL or tPHI are 0.1ns an maximum value are 3.3ns. The SN74AVC16T245 minimum are 0.5ns and maximum are 3.3ns too. What character decide the 2T245 data rate is up to 500Mbps but 16T245 is only 380Mbps. The typical value? but it is not shown in the datasheet.

    If I use SN74AVC2T245. It sill has potential risk to get 303Mbps data rate for some poor chip, right?

    Regards,
    Shu

  • To repeat my first answer: The propagation delay gives you only a pessimistic estimate. The internal circuit is a little bit pipelined; you can apply a new voltage at the input buffer even when the output buffer has not yet finished switching.

    Anyway, using LVDS buffers appears to be the simplest solution.

  • Hi Clemens,

    I understand the solution. now i am only wonder how the maximum data rate come from? The 500Mbps and 380Mbps only are described in first feature section. There is no specific character to support this value. I wish to evaluate this feature in right way to avoid make mistake in the future design. Should I trust that data rate desperation completely? So how could I evaluate the chip without data rate description as SN74LVC8T245 or SN74LVC16T245?

    Regards,
    Shu

  • Modern devices like the SN74LXC2T45 or TXU0204 specify the data rate in the datasheet. For older devices, you have to find that information somewhere, or use the conservative estimate derived from the propagation delay.

  • Hi Clemens,

    Thank you very much.

    I have another question to bother you. it is about the input/output rise and fall time. why there is no such characteristic in any datatsheet of level translator. I think that may impact the data rate too, or do i make a mistake? Is It englected because the small value compare to the propagation delay? If my contorller can generate a signal with 500ps rise/fall time. Does the level translator can react it with similar rise/fall time?

  • Both the inputs and outputs are buffered, so the rise/fall times are independent of each other. (This is different from analog devices like comparators.)

    CMOS inputs (except Schmitt-trigger inputs) have a maximum rise/fall time; see the Δt/Δv specification. But they switch when the voltage reaches the switching threshold (somewhere between VIL and VIH). The output rise/fall time depends only on the drive strength and the capacitive load.

  • Hi Wang,

    Similar to Clemens' feedback, please do not try to correlate the propagation delay to the data rate specifications for these devices, thanks.

    Best Regards,

    Michael.

  • Thank you Clemens and Michael. That make sense.

    Shu

  • Hi Wang,

    To properly close this E2E thread, please help resolve if no further concerns, thanks.

    Best Regards,

    Michael.