setting default input logic levels for the SN74LVC8T245

Anand Jog

Other Parts Discussed in Thread: SN74LVC8T245, SN74LVCH8T245

Hi All,

The SN74LVC8T245 datasheet specifies that input circuitry for both ports A and B is always active and requires a logic level (high or low) to be applied. Does this mean

1. Pins at ports A and B cannot be left floating even when outputs are disabled OE = 1?

2. Are there example circuits for this chip, an application note etc.?

3. If current consumption does rise due to floating A and/or B ports will it revert to normal if valid logic levels are presented to the inputs? That is, is the high ICC, or ICCZ a temporary feature that does not require the SN74LVC8T245 to be power cycled in the event of high ICC or ICCZ?

Thanks!

Anand

over 14 years ago

0 Hattie over 14 years ago

TI__Genius 9085 points

You may want to consider the SN74LVCH8T245. This device has bus-hold circuitry which eliminates the need for pull-up or pull-down resistors.

1. Yes, there is still a risk of increased current consumption if the IOs are disabled with the OE pin.

2. Below is an application note on floating cmos input -

http://focus.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=scba004c

3. The excess current consumption would be only temporary. Once a valid logic level is established on the IO, the current would return to normal.

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setting default input logic levels for the SN74LVC8T245