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SN74AUP1G125: SN74AUP1G125 (Buffer-3 State) output abnormal issue.

Vincent Lin
Prodigy 240 points
Part Number: SN74AUP1G125
Other Parts Discussed in Thread: SN74AUP1G32, SN74AUP1G97

Dear Sir:

SN74AUP1G125 (Buffer-3 State) output abnormal issue.

1.The input(OE\) of SN74AUP1G125 (Buffer-3 State) is Low.

(1) Rise:

The input(A) of SN74AUP1G125 (Buffer-3 State) rise time doesn't exceed the Δt/Δv Input transition rate max.(200ns/V).

The output(Y) of SN74AUP1G125 (Buffer-3 State) rise time is shorter than the propagation delay.

(2) Fall:

The input(A) of SN74AUP1G125 (Buffer-3 State) fall time doesn't exceed the Δt/Δv Input transition rate max.(200ns/V).

The output(Y) of SN74AUP1G125 (Buffer-3 State) fall time is shorter than the propagation delay.

 

2.The input(A) of SN74AUP1G125 (Buffer-3 State) Keep High.

The input(OE\) of SN74AUP1G125 (Buffer-3 State) change from High to Low.

The input(OE\) of SN74AUP1G125 (Buffer-3 State) doesn't exceed the Δt/Δv Input transition rate max.(200ns/V).

The output(Y)(Buffer Pin4) of SN74AUP1G125 (Buffer-3 State) rise time is shorter than the propagation delay.

 

3.The input(A) of SN74AUP1G125 (Buffer-3 State) Keep High.

The input(OE\) of SN74AUP1G125 (Buffer-3 State) change from Low to High.

The input(OE\) of SN74AUP1G125 (Buffer-3 State) doesn't exceed the Δt/Δv Input transition rate max.(200ns/V).

The output(Y)(Buffer Pin4) of SN74AUP1G125 (Buffer-3 State) fall time is longer than the propagation delay.

The fall time is micro-second(us) level very longer.

Why is the output(Y)(Buffer Pin4) of SN74AUP1G125 (Buffer-3 State) fall time so longer?

Is it normal?

Please check to reply it asap.

Thanks a lot.

Best regards

Vincent

  • 0
    Guru 316600 points

    When the output is disabled, it is not driven to any voltage, i.e., it is floating. You must not try to measure the voltage in this case. (See [FAQ] What's the difference between logic output types (push-pull, open-drain, 3-state)?)

    If you want to have a known voltage even when the output is disabled, then you must add a pull-up or pull-down resistor, and the rise/fall time is determined by the value of this resistor.

  • 0 in reply to Clemens Ladisch
    Prodigy 240 points

    Dear Sir:

    1.When the output is disabled, it is not driven to any voltage, i.e., it is floating. You must not try to measure the voltage in this case. (See [FAQ] What's the difference between logic output types (push-pull, open-drain, 3-state)?)

    --> The input(OE\) of SN74AUP1G125 (Buffer-3 State) change from Low to High.( output is disabled )

    The output(Y)(Buffer Pin4) of SN74AUP1G125 (Buffer-3 State) fall time is longer than the propagation delay.

    Is it normal?

    2.If you want to have a known voltage even when the output is disabled, then you must add a pull-up or pull-down resistor, and the rise/fall time is determined by the value of this resistor.

    --> Please provide us with the pull-down resistor range.

    The output(Y)(Buffer Pin4) of SN74AUP1G125 (Buffer-3 State) fall time exceed the Δt/Δv Input transition rate max.(200ns/V).

    How to improve it to meet the Δt/Δv Input transition rate max.(200ns/V)?

    3.  The output(Y)(Buffer Pin4) of SN74AUP1G125 (Buffer-3 State) connects to the input of OR Gate (SN74AUP1G32).

    Cannot the connection of schematic use?  Does it have problem?

    Please check to reply us asap.

    Thanks a lot.

    B.R

    Vincent

  • 0 in reply to Vincent Lin
    Guru 316600 points

    1. Yes.

    2. The pull-down resistor and any capacitances on the board form a low-pass filter. So the value of the resistor depends on the board.

    3. If you want a faster fall time, do not disable the output but drive the output low. This is and AND gate with one inverted input, which can be implemented with the SN74AUP1G97 (which already has Schmitt-trigger inputs).

  • 0 in reply to Clemens Ladisch
    Prodigy 240 points

    Dear Sir:

    If you want a faster fall time, do not disable the output but drive the output low. This is and AND gate with one inverted input, which can be implemented with the SN74AUP1G97 (which already has Schmitt-trigger inputs).

    1.It means:

    Use SN74AUP1G97 (which already has Schmitt-trigger inputs) instead of SN74AUP1G125 (Buffer-3 State).

    Is it correct?

     

    2.SN74AUP1G97 (which already has Schmitt-trigger inputs) is always active.( Can not disable it).

    The output(Y) of SN74AUP1G97 fall time doesn’t exceed tpd 8.8ns (propagation delay).

    The output(Y) of SN74AUP1G97 connects to the input of OR Gate (SN74AUP1G32).

    The output(Y) of SN74AUP1G97 fall time can meet OR Gate (SN74AUP1G32)Δt/Δv Input transition rate max.(200ns/V).

    Is it correct?

    [ SN74AUP1G97 (which already has Schmitt-trigger inputs)

    VCC = 3V ( 3.3 V ± 0.3 V ) , tpd(Max) = 8.8ns. 

    The Output Rise/Fall Time.(max) value doesn't exceed the 8.8ns.]

    Please check to reply us asap.

    Thanks a lot.

    Best regards,

    Vincent

  • 0 in reply to Vincent Lin
    Guru 316600 points

    Yes to all questions.