This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74LVC2G125: Dual Bus Buffer Gate With 3-State Outputs

Part Number: SN74LVC2G125
Other Parts Discussed in Thread: SN74AUP2G125, , , SN74AUP2G34, ISO7762

Hello,

I have MISO signal which works at 13.5MHZ 

Whose 

Trise: 1.5nS

Tfall: 1.5 nS

Total ON time: 36nS

MISO Signal Frequency: 13.5MHZ

Voltage: 3.3V

Can you please suggest Dual Bus buffer gate for my applications?

  • Hi Deepak,

    Thanks for the detailed information. There's one thing missing though - what's the load that is to be driven?

    If you're driving a 12 cm or less trace with 30pF or less total load capacitance, I would recommend using any of these options:

    For devices that can be disabled (output set to high-impedance):

    SN74AUP2G125

    SN74LVC2G125

    SN74LVC2G125-Q1 (same as above, just automotive qualified)

    For devices that cannot be disabled (always drive either high or low at output):

    SN74AUP2G34

    SN7LVC2G34

    There are actually many more options, but those would just be my top picks. The AUP parts have smoother output transitions (less EMI) and use less power, while the LVC parts have higher drive strength.

    Here's a filtered list of 2 to 8 channel devices that would likely work in this application:

    https://www.ti.com/logic-voltage-translation/buffers-drivers-transceivers/noninverting/products.html#p0min=-0.5;3.3&p0max=3.3;18&p480=2;8 

  • Hi Emrys,

    Thanks for answer.

    Please find attached Skeleton

    Here, I have used ISO7762 in multiple slave configuration, But due to output nature of ISO7762--> MISO1 Signal Pulling down due to other ISO7762 and viceversa and we are not getting SPI Slave response (MISO).

    Now to solve this, We need to have Buffer which would work here and it should not pulled down other signals so Buffer is better option here? you could suggest if you have good ideas?

    SPI Clock frequency is 13.5MHZ.

  • If the two slave devices use the same ground, you could combine their MISO signals before the isolator.

    In the architecture shown in you image, you need buffers with three-state outputs. Use any of the proposed '2G125 devices for active-low control signals, or '2G126 for active-high control signals.

  • Hi Clemens,

    Thanks for reply.

    No common GND before Isolator, That reason we shorted after isolator.

    Mostly Active low signal devices would be prefereble so both can drive with the help of Chip selects signals.

    What is your opinion?

  • Use any '125 buffer.