SN74HCS74: Clock edge issue

tyrael cui

Intellectual 285 points

Part Number: SN74HCS74
Other Parts Discussed in Thread: SN74LVC1G00, SN74LVC1G132

Hi Logic Experts,

I'm using the sn74HCS74 to control power on/off. Below is my schematic.

The clock signal is drived by the output of the SN74LVC1G00。

Here is the problem I met:

The Q output is changed by both rising-edge and falling-edge clock signal !

The circuit works well after I replaced the SN74LVC1G00 with the SN74LVC1G132.

Apparently the problem caused by the clock signal.But I got confused! Why is that,since the SH74HCS74 inputs allow for slow or noisy input
signals?

Thanks!

Tyrael

over 2 years ago

0 Clemens Ladisch over 2 years ago

Guru 278800 points

The output signal of a digital gate always has fast edges.

The '132 device has Schmitt-trigger inputs, the '00 has not. So there is a problem with the input signal of that gate. Which you have not shown in the schematic.

0 tyrael cui over 2 years ago in reply to Clemens Ladisch

Intellectual 285 points

Thanks for your reply!

Here is my schematic

The signal RTCINT is an output of RTC alarm interrupt,GH1248 is a magntic switch IC which outputs low level when actived.

The signal PWRCON comes from an MCU pin.

+1 Clemens Ladisch over 2 years ago in reply to tyrael cui

Guru 278800 points

When PWRCON changes, the rising edge of the signal at the B input of U5 will be very slow because the voltage is pulled up weakly through R4. (The falling edge might also be slow because of R6.) This will lead to oscillations if U5 does not have Schmitt-trigger inputs.

0 tyrael cui over 2 years ago in reply to Clemens Ladisch

Intellectual 285 points

Clemens Ladisch said:
When PWRCON changes, the rising edge of the signal at the B input of U5 will be very slow because the voltage is pulled up weakly through R4. (The falling edge might also be slow because of R6.) This will lead to oscillations if U5 does not have Schmitt-trigger inputs.

Hi,Clemens,

I can see what you mean ,the slow edge input signal could cause the abnormal clock signal output.

However there's something I can't understand yet.Below are the signal waveforms of SN74HCS74.

the rising-edge of clock

the falling-edge of clock

The yellow signal is clock,the green signal is Q~。

The waveform of clock signal looks fine from the screenshot,and the output of SN74HCS74 still changed on the falling edge clock signal.

Thanks for your patience !

+1 Clemens Ladisch over 2 years ago in reply to tyrael cui

Guru 278800 points

The sample rate is too low to see oscillations. Use 1 GSa/s, if possible.

0 tyrael cui over 2 years ago in reply to Clemens Ladisch

Intellectual 285 points

The waveform of clock signal testified your opinion.

Appreciate your help!!

Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

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SN74HCS74: Clock edge issue