SN74LVC1G123 Timing infromation

Ted Brannan

Other Parts Discussed in Thread: SN74LVC1G123

Hello,

The enable/disable timing information for this device are not published in the datasheet. I searched the forum and found another similar post for the 138, but no solution response. Can you please provide the enable and disable timing information from Ioff, as well as any pertinent state information.

Thanks!

Ted

ref pages 8 and 9 of SN74LVC1G123 datasheet, SCES586B

over 14 years ago

0 Fernando over 14 years ago

Prodigy 90 points

I need a help. Please see a page 3 in datasheet "REQUIRED TIMING CIRCUIT". Should the Cext be connected to GND? If yes, what there is a Cext pin for?

You can see this document where Cext pin not connected to GND. What is correct?

Can SN74LVC1G123 generate so much pulse like a 2 seconds? Will the 200k and 2.2u values be close to this time?

0 Chris Cockrill over 14 years ago in reply to Fernando

TI__Mastermind 46480 points

The enable disable timing on page 8 and 9 do not pertain to this part. That is a generic table used for all parts. There is no enable disable pin on the 1g123.

The Cext pin is an internal gnd so you can tie to either gnd or Cext pin.

I beleive it should do 2 seconds 200k and 10uf.

0 Ted Brannan over 14 years ago in reply to Chris Cockrill

Prodigy 30 points

Thanks Chris for finally responding to this post.

I know that there is no enable/disable pin on this device, but the device does feature the "Ioff" function. My question relates to the enable/disable timing when using the Partial power down mode. The datasheet also seems to be missing information pertaining to the RC thresholds and/or an applications section that includes an equation for setting the timing parameters. I needed to derive the equation myself (not hard), but IMO it should be there.

Thanks!

Ted

0 Fernando over 14 years ago in reply to Chris Cockrill

Prodigy 90 points

Chris Cockrill said:
I beleive it should do 2 seconds 200k and 10uf.

I fear that the chip can be destroyed by the discharge current. What do you think?

0 Chris Cockrill over 14 years ago in reply to Fernando

TI__Mastermind 46480 points

Hi Fernando

Yes you may be correct that the 10uf may be pushing it. You may need to adjust the resistor more and capacitor less. I have seen these parts used for timings over 1s so I believe they can do 2s. At some point the resistor will get large enough that it does not make any difference. So you will need to breadboard your circuit.

I did notice there was no formula in the datasheet. I will have one added.

Ioff is a feature of power down and we have never measured the timing as far as I know. This timing is related to how quickly Vcc reaches 0V.

0 Fernando over 14 years ago in reply to Chris Cockrill

Prodigy 90 points

Chris Cockrill said:
Yes you may be correct that the 10uf may be pushing it

So What should I do? Can you please give me your formula?

0 Chris Cockrill over 14 years ago in reply to Fernando

TI__Mastermind 46480 points

resistance times capacitance = Pulse width

0 Ed Hann over 12 years ago in reply to Chris Cockrill

Prodigy 20 points

The data sheet does not give any indication of timing accuracy. We are looking at a 15uS pulse using 1.5K and 0.01uf. Equivalent parts indicate about +/-10% accuracy (not including R and C tolerance). Is your part the same?

0 Rolf Veen over 11 years ago in reply to Chris Cockrill

Prodigy 30 points

Can the Cext pin be left open and connect the capacitor directly to ground ?

0 Jose Maroto over 11 years ago in reply to Rolf Veen

TI__Expert 3580 points

Hi Rolf,

As per datasheet page 3, the required timing circuit shows that Cext should be connected to GND.

Krgds

0 Rolf Veen over 11 years ago in reply to Jose Maroto

Prodigy 30 points

Hi, Jose Luis. I think, based on this quote, that the what the datasheet tells is not the only option:

Chris Cockrill said:

The Cext pin is an internal gnd so you can tie to either gnd or Cext pin.

But I cannot deduce from that info if Cext can be left unused, hence my question.

Kind regards

Logic

Logic forum

SN74LVC1G123 Timing infromation