SN54HC595: Timing of output for cascaded shift registers

BOb Wagner

Part Number: SN54HC595
Other Parts Discussed in Thread: SN74HC164

Thanks so much for forums input on the earlier questions on the 54HC595 8-bit shift register. I wanted to ask a related question that addresses the timing of the pulses that output from two cascaded shift registers when the QH’ output is fed into the SER input from the next shift register.

From the timing diagram in the data sheet the output Qb is 1 clock cycle later than Qa, and the output Qc is one clock cycle later than Qb and so on. Qh’ is one half a clock cycle ahead of Qh. So if I feed Qh’ into the SER line of the next shift register, this pulse will come out one clock pulse later at Qa2. So if I line up Qa to Qh, from the first shift register, and Qa2 from the second shift register my thought is that Qa2 from the second shift register won’t be 1 clock cycle away from Qh on the first shift register because it is one half a clock cycle ahead of the last output from the first shift register. So if I want one clock cycle separation between data between cascaded shift registers for the 54HC595 should I be sending Qh’ into the next shift register, or possibly use Qh. I apologies in advance from taking up so much of the TI forum bandwidth. Thanks, Bob Wagner

over 2 years ago

0 Emrys Maier over 2 years ago

TI__Guru* 97046 points

Hey Bob,

We're always happy to help. The datasheet timing diagram shows RCLK operating 180 degrees out of phase with SRCLK, which is not really the most common method of using this device - but it is an easy way to fit a lot of data in a small space for the datasheet timing diagram. RCLK is typically only pulsed once to push the internal registers to the output registers.

I think this app note may help you a great deal: Designing with Shift Registers

I think this simplified block diagram has helped me a great deal in understanding and using the '595 shift register function.

In the normal method of using a '595, the shift registers operate independent of the outputs. Above you can see how the internal registers cycle through without affecting the output registers at all through the yellow data path - they are controlled by SRCLK. The outputs are loaded by pulsing RCLK.

If you short together RCLK and SRCLK, the outputs will always be exactly one clock cycle behind the internal registers.

If you're looking for a device to just cycle data through the outputs directly, I'd recommend using the SN74HC164 instead - it's much simpler (also covered in the above mentioned app note).

Please let me know if I can be of further assistance.

Logic

Logic forum

SN54HC595: Timing of output for cascaded shift registers