Logic gate output status during power on

user4090349

Intellectual 941 points

Other Parts Discussed in Thread: SN74LVC1G125

Hello

Does the logic gate like LVC1G08 have the POR?

During power on process, maybe from 1.2~1.65V, does the gate output High-Z?

Could you please help clarify this?

over 2 years ago

+1 Emrys Maier over 2 years ago

TI__Guru* 97046 points

Hello,

user4090349 said:
Does the logic gate like LVC1G08 have the POR?

No, POR is used for clocked devices to provide a known operating state at startup - AND gates are combinational logic, and as such do not require a reset signal to be initialized.

user4090349 said:
During power on process, maybe from 1.2~1.65V, does the gate output High-Z?

The device's operation is only defined at VCC = 0V and VCC = 1.65V to 5.5V. Between these values, we don't specify operation.

That being said, typically a CMOS gate will start to act like a gate around 1 to 1.5V. Below that, the MOSFETs won't have enough bias voltage to function.

0 user4090349 over 2 years ago in reply to Emrys Maier

Intellectual 941 points

Hello Emrys

Thanks for your quick feedback.

Does that mean, in the power off period, when the supply voltage falls below 1.65V.

The behavior of the gate could not be predicted. It could output high level/low level and we do not know what will happen.

Maybe same for the power on period, before the supply voltage rise above 1.65V, we could not predict what will happen.

Thanks!

0 user4090349 over 2 years ago in reply to Emrys Maier

Intellectual 941 points

I don't want maybe a delay after 1.65V. I want to know if the gate is not supplied with enough voltage, what will happen?

0 Clemens Ladisch over 2 years ago in reply to user4090349

Guru 316440 points

Above 0 V and below 1.65 V, the device might output a wrong value.

Only devices (e.g., SN74LVC1G125) with an /OE input pulled high are guaranteed to have an Hi-Z output during power up/down.

0 user4090349 over 2 years ago in reply to Clemens Ladisch

Intellectual 941 points

Do you mean for SN74LVC1G125, it is Hi-Z output when supply between 0V~1.65V.

Or is there a method to make the output of SN74LVC1G125 Hi-Z when supply is between 0V~1.65V?

0 Clemens Ladisch over 2 years ago in reply to user4090349

Guru 316440 points

The '125 output is guaranteed to be Hi-Z only when /OE is high.

0 user4090349 over 2 years ago in reply to Clemens Ladisch

Intellectual 941 points

Is the OE of 125 internally pull up during power up or we must connect a pull up resistor to make it Hi-Z during power on & power off.

+1 Clemens Ladisch over 2 years ago in reply to user4090349

Guru 316440 points

As mention in section 9.1 of the datasheet, it needs an external pull-up.

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Logic gate output status during power on