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CD74HCT40105: MASTER RESET (MR) Pulse Timing.

Part Number: CD74HCT40105

Dear, support team.

In the data sheet of "CD74HCT40105", the Master Reset signal states that it is reset by inputting a pulse signal.
Please tell me the details of the pulse signal.

・Low time from power ON to rise of MR signal
・If the power ON and MR signal rise timings are the same, will the reset be enabled only by the fall of the MR signal?
*In the specifications, the time for the High section of the reset pulse is described, but I couldn't find it for Low.

Best Regards,
Hiroaki Yuyama

  • Hello Yuyama-san,

    In the data sheet of "CD74HCT40105", the Master Reset signal states that it is reset by inputting a pulse signal.
    Please tell me the details of the pulse signal.

    The MR input is level controlled, but requires a minimum pulse width to properly operate.

    You can see the exact logic functionality here:

    In the "Prerequisites for Switching" section of the datasheet, the minimum pulse width for the MR input is defined:

    ・Low time from power ON to rise of MR signal

    This is not a specification of the device.

    I would recommend providing at least the maximum propagation delay time provided in the datasheet before beginning operation, as the device may have unknown internal states at startup and this is the minimum time to ensure all states have stabilized.

    For 2-V operation, this would be 3750 ns.

    ・If the power ON and MR signal rise timings are the same, will the reset be enabled only by the fall of the MR signal?
    *In the specifications, the time for the High section of the reset pulse is described, but I couldn't find it for Low.

    No, the MR input is level triggered, it is not edge triggered or pulse-width triggered. As long as the MR pin is held HIGH while the supply is within the recommended operating voltage range and the minimum pulse width is provided, then the device's memory will be cleared. Note my answer above in regards to allowing the device to stabilize prior to starting operation.

  • Hello Emrys-san,

    Thank you for your answer.

    We understand that the CD74HCT40105 master reset input is level triggered, it is not edge triggered or pulse-width triggered.
    What is important in our advice to customers is how long it should take to turn on the MR signal after the power is turned on.
    Is it okay to provide at least the maximum propagation delay time provided in the datasheet before beginning operation as you suggested?
    For example, with a 5V power supply, the recommended time is only about 700nsec.

    The background of the question is to replace the FIFO register IC SN74LS224N with CD74HCT40105E, which Owen-san advised.
    CD74HCT40105: Replace SN74LS224 with CD74HCT40105 - Logic forum - Logic - TI E2E support forums

    Currently, the rise timing of the master reset signal and the power input timing to the CD74HCT40105 are almost the same, and the above time cannot be secured.
    We are guessing that "it is not working properly because the reset is not working properly".
    Therefore, we are considering a reset signal input that satisfies the above specifications.

    Best Regards,
    Hiroaki Yuyama

  • Hello Yuyama-san,

    Yes, my recommendation can be given to the customer. Please note that this is a public forum - all of my advice is available to all customers from here, and I will not post something that I do not recommend to tell to the customer.

  • Hello Emrys-san,

    Thank you for your qualified advice.
    I was very cautious because the data sheet for the CD74HCT40105 did not specify the rising edge of the MR reset after power-on.
    Thank you for your support !

    Best Regards,
    Hiroaki Yuyama