Hello,
I am using the SN74HC165 as a port expander - where in each SN74HC165 is connected to 8 inputs. I am using the serial interface to communicate with the part - the schematic is as follows:
My logic is as follows:
1. When is the Slave Select is idle (high) - SH/nLD will be low. This will enable constant sampling of the parallel inputs. Clock input is ignored during this time.
2. When the Slave select is asserted (low) - SH / nLD will be high. This will enable the serial data to be transmitted out.
The problem however, is that when I use two chips the data out line is constantly held low. My assumption is that since these parts drive the data output, the deselected part holds the data line low. I do need to mention that I have been successfully able to read the input signals when I use single chip.
Can someone please confirm my hypothesis and if true can you please suggest a solution.
Thank you
Regards
Santhosh
